4-Port PoE Manager

Microsemi Proprietary and Confidential. PD69104B1/F Datasheet Revision 2.0

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3.14

I²C High-Level Layer

The following diagram describes the supported I²C high-level packet structure.

Figure 4 • High-Level Packet Structure

3.14.1

Byte/Word Read/Write Transaction

The first byte is the control byte that consists of the chip address and a read/write operation

indication.

The second byte is the internal chip's address register.

The following bytes/words are data bytes. In case of a read operation, they are read from the slave,

and in case of a write operation, they are written to the slave.

3.14.2

Successive Read/Write Transaction

The master can continue sending bytes that the slaves write, or continue receiving data from a slave

during the address phase.

The slave will continue to send/receive data bytes from/to the master until a 'stop bit' is asserted by

the master.

Each byte received by the slave (or each byte to be read from the registers) is received from the next

register address (each byte address is increased by 1).

3.14.3

Read Byte Transaction

The slave supports a 'send byte' transaction.

The master begins with a start bit. The following byte consists of the chip address and a read bit.

If the chip address is correct, the slave acknowledges the byte and immediately (at the next sck

phase) sends a data byte from a constant address (addr 7'h00).

A send byte transaction continues with successive read transactions (address 1, address 2, and so

on) until the master asserts a stop bit.

3.14.4

Broadcast Support

All slaves answer a general address sent by the master. In case of semi-auto modes, the general address

is 7'h30, and in case of MSCC Extended Auto mode, the general address is 7'h0.

The broadcast is for master writing only; read access is ignored in a broadcast transaction.

3.14.5

Timeout Mechanism

The I²C has an internal counter of 14 ms. The counter resets each time the SCL rises or falls. If the SCL is

“stuck” for 14 ms, the I²C returns to IDLE state and transaction is ignored (the timeout mechanism is

active between the start bit and the stop bit).