4-Port PoE Manager

Microsemi Proprietary and Confidential. PD69104B1/F Datasheet Revision 2.0

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7

Application Information

PD69104B1/F meets IEEE 802.3af and IEEE 802.3at functionality standards, as well as legacy (capacitor)

and Cisco’s PDs detection standards. Moreover, it supports additional protections such as short circuit,

and dV/dT protection upon port startup.

7.1

Line Detection

The line detection feature detects a valid AF or AT load, as specified in the IEEE 802.3 standard. The

resistance value should range from 19 kΩ to 26.5 kΩ. Line detection is based on four different voltage

levels generated over the PD (the load), as shown in the following illustration.

Figure 17 • Typical PoE Voltage vs. Time Diagram

The first 2 levels (low voltage level < 3 V) are for detecting if load up to 200KΩ is connected to the PSE;

preventing from applying high voltages on the PSE when there is no-load, and eliminating potential risk

to the DTE. If first detection passes next 2 levels of resistor detection are applied. If the POE detects a

valid resistor signature value the detection is passed else the detection fails and moves to IDLE.

7.2

Legacy (Cap) Detection

In case pin 36 (RES_CAP / INT_OUT) is set to “0”, the detection mechanism of PD69104B1/F is

configured to detect and power LEGACY PDs, as well as AF/AT compliant PDs.

This mechanism also detects and powers CISCO Legacy PDs.

7.3

Classification

The classification process takes place right after the resistor detection is successfully completed. The

main goal of the classification process is to detect the PD class, as specified in the IEEE 802.3AF and AT

standards. The process is being done by applying a voltage to the PD nodes and measuring the port

current.

In the AF mode the classification mechanism is based on a single-voltage level step (single finger).

In the AT mode classification mechanism is based on two-voltage level steps (dual finger), as defined in

the IEEE 802.3at standard.

7.4

Port Startup

Upon a successful detection and classification process, power is applied to the load via a controlled

startup mechanism.

During this period current is limited to 425 mA for a typical duration of 65 ms. This enables the PD load