4-Port PoE Manager

Microsemi Proprietary and Confidential. PD69104B1/F Datasheet Revision 2.0

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startup mechanism.

During this period current is limited to 425 mA for a typical duration of 65 ms. This enables the PD load

to charge and to enter a steady state power condition.

7.5

Over-Load Detection and Port Shut Down

After power up, PD69104B1/F automatically initializes its internal protection mechanisms. These

mechanisms are utilized to monitor and disconnect the power from the load in case of an extreme

conditions scenario. Scenarios such as over-current or short ports terminals, as specified in the IEEE

802.3AF/AT standard.

7.6

Disconnect Detection

PD69104B1/F supports the DC Disconnect function as per the IEEE 802.3AF/AT standard.

This mechanism continuously monitors the load current and disconnects the power in case it drops

below 7.5 mA (typical) for more than 322 ms.

7.7

Over-temperature Protection

PD69104B1/F has internal temperature sensors that continuously monitor the junction temperature and

set alarm bit when exceeds 120 °C or disconnect load power when it exceeds 200 °C. This mechanism

protects the device from extreme events, such as high ambient temperature or other thermo-

mechanical failures that may damage the PD69104B1/F device.

The Alarm threshold can be set by register.

7.8

V MAIN Out of Range Protection

The PD69104B1/F automatically disconnects the ports power when V

exceeds 58.5 V threshold (with

main

180 mV hysteresis) or drops below 40 V threshold (with 180 mV hysteresis). This extremely valuable

feature protects the load in case the main power source is faulty or damaged.

7.9

Serial EEPROM Load Mechanism

The PD69104B1/F is capable of loading its registers values from an external serial EEPROM during a boot

slot time.

To utilize the EEPROM boot, the COMM_MODE pin must be set to E2PROM_MODE (not connected).

The following is a list of features for the PD69104B1/F device.

MASTER I²C communication.

7 bit addressing

250KHz frequency

EEPROM constant address: 7'hA0

EEPROM must support read byte and read after read

Two repeated transactions in case the EEPROM does not acknowledge the transaction

A FIR filter for glitches cancelling

There are 5 consecutive read transaction (master transactions) made by the PD69104B1/F for reading

data from the EEPROM and uploading it to the PD69104B1/F registers.

The first transaction reads all registers from address 8'h70 to address 8'h9F.

The second transaction reads registers HPEN and HPMD1 (from addresses 8'h44 and 8'h46).

The third transaction reads register HPMD2 (from address 8'h4b).

The fourth transaction reads register HPMD3 (from address 8'h50).

The fifth transaction reads register `mp_hpmd4 (from address 8'h55).

The following illustration shows the read transaction format.