4-Port PoE Manager

Microsemi Proprietary and Confidential. PD69104B1/F Datasheet Revision 2.0

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Figure 3 • Packet Structure

3.13.1

Address Phase

This phase, is common to both read and write accesses.

Both accesses (read and write) begin with a START indication.

The address of the slave is following the START indication. In case of a miss match, the slave ignores

the rest of the access and waits for the 'STOP' indication to close the current access. However, in

case the slave address matches, the next bit indicates the type of the access (read or write).

The matched slave acknowledges the first byte.

The following byte is the internal register address. The slave should acknowledge the byte.

3.13.2

Data Phase

In this phase the read and write accesses behave differently.

Write access

Byte of write data is transmitted to the slave; the slave acknowledges it.

A stop indication from the master closes the current access.

Read access

Another command byte is received, comprised of the slave address and the real command type

(in this case read). The slave acknowledges the byte.

At this stage, the master is ready to continue the communication and to sample the read data;

hence, the read data must be ready on the next rise of the clock pulse.

A byte of data is transmitted to the master; the master acknowledges it.