CSD97396Q4M

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SLPS572 – DECEMBER 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The Power Stage CSD97396Q4M is a highly optimized design for synchronous buck applications using NexFET

devices with a 5 V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest

power loss and highest system efficiency. As a result, a rating method is used that is tailored towards a more

systems centric environment. The high-performance gate driver IC integrated in the package helps minimize the

parasitics and results in extremely fast switching of the power MOSFETs. System level performance curves such

as Power Loss, SOA, and normalized graphs allow engineers to predict the product performance in the actual

application.

8.2 Typical Application

Figure 3. Application Schematic

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