CSD97396Q4M

SLPS572 – DECEMBER 2015

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7 Detailed Description

7.1 Overview

The CSD97396Q4M NexFET™ Power Stage is a highly optimized design for use in a high-power, high-density

synchronous buck converter.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Powering CSD97396Q4M and Gate Drivers

An external VDD voltage is required to supply the integrated gate driver IC and provide the necessary gate drive

power for the MOSFETs. A 1 µF 10 V X5R or higher ceramic capacitor is recommended to bypass VDD pin to

PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap supply

to drive the Control FET is generated by connecting a 100 nF 16 V X5R ceramic capacitor between BOOT and

BOOT_R pins. An optional RBOOT resistor can be used to slow down the turn on speed of the Control FET and

reduce voltage spikes on the VSW node. A typical 1 Ω to 4.7 Ω value is a compromise between switching loss

and VSW spike amplitude.

7.3.2 Undervoltage Lockout (UVLO) Protection

The UVLO comparator evaluates the VDD voltage level. As VVDD rises, both the Control FET and Sync FET

gates hold actively low at all times until VVDD reaches the higher UVLO threshold (VUVLO_H)., Then the driver

becomes operational and responds to PWM and SKIP# commands. If VDD falls below the lower UVLO threshold

(VUVLO_L = VUVLO_H – Hysteresis), the device disables the driver and drives the outputs of the Control FET and

Sync FET gates actively low. Figure 1 shows this function.

CAUTION

Do not start the driver in the very low power mode (SKIP# = Tri-state).

6

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