CSD97396Q4M

SLPS572 – DECEMBER 2015

www.ti.com

Feature Description (continued)

Table 1 shows the logic functions of UVLO, PWM, SKIP#, the Control FET Gate and the Sync FET Gate.

Table 1. Logic Functions of the Driver IC

UVLO

PWM

SKIP#

SYNC FET GATE

CONTROL FET GATE

MODE

Active

—

—

Low

Low

Disabled

Inactive

Low

Low

High(1)

Low

DCM(1)

Inactive

Low

High

High

Low

FCCM

Inactive

High

H or L

Low

High

Inactive

Tri-state

H or L

Low

Low

LQ(2)

Inactive

—

Tri-state

Low

Low

ULQ(3)

(1)

Until zero crossing protection occurs.

(2)

Low quiescent current (LQ)

(3)

Ultra-low quiescent current (ULQ)

7.3.4.1 Zero Crossing (ZX) Operation

The zero crossing comparator is adaptive for improved accuracy. As the output current decreases from a heavy

load condition, the inductor current also reduces and eventually arrives at a valley, where it touches zero current,

which is the boundary between continuous conduction and discontinuous conduction modes. The SW pin detects

the zero-current condition. When this zero inductor current condition occurs, the ZX comparator turns off the

rectifying MOSFET.

7.3.5 Integrated Boost-Switch

To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the

conventional diode between the VDD pin and the BST pin is replaced by a FET which is gated by the DRVL

signal.

7.4 Device Functional Modes

Table 1 shows the different functional modes of CSD97396. The diode emulation mode is enabled with SKIP#

pulled low, which improves light load efficiency. With PWM in tri-state, Power Stage enters LQ mode and the

quiescent current is reduced to 130 µA. When SKIP# is held in tri-state, ULQ mode is enabled and the current is

decreased to 8 µA.

8

Submit Documentation Feedback

Copyright © 2015, Texas Instruments Incorporated