CSD97396Q4M

SLPS572 – DECEMBER 2015

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9 Layout

9.1 Layout Guidelines

9.1.1 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and

thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below

is a brief description on how to address each parameter.

9.1.2 Electrical Performance

The CSD97396Q4M has the ability to switch at voltage rates greater than 10 kV/µs. Special care must be then

taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.

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The placement of the input capacitors relative to VIN and PGND pins of CSD97396Q4M device should have the

highest priority during the component placement routine. It is critical to minimize these node lengths. As such,

ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 16).

The example in Figure 16 uses 1 × 1 nF 0402 25 V and 3 × 10 µF 1206 25 V ceramic capacitors (TDK Part #

C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an

appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power

Stage C5, C8 and C6, C19 should follow in order.

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The bootstrap cap CBOOT 0.1 µF 0603 16 V ceramic capacitor should be closely connected between BOOT

and BOOT_R pins

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The switching node of the output inductor should be placed relatively close to the Power Stage

CSD97396Q4M VSW pins. Minimizing the VSW node length between these two components will reduce the

PCB conduction losses and actually reduce the switching noise level. (1)

9.2 Layout Example

Figure 16. Recommended PCB Layout (Top Down View)

9.3 Thermal Considerations

The CSD97396Q4M has the ability to use the GND planes as the primary thermal path. As such, the use of

thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder

voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount

of solder attach that will wick down the via barrel:

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Intentionally space out the vias from each other to avoid a cluster of holes in a given area.

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Use the smallest drill size allowed in your design. The example in Figure 16 uses vias with a 10 mil drill hole

and a 16 mil capture pad.

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Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and

manufacturing capabilities.

(1)

Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of

Missouri – Rolla

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