UDG-12218

VUVLO_H

VUVLO_L

VVDD

Driver On

CSD97396Q4M

www.ti.com

SLPS572 – DECEMBER 2015

Feature Description (continued)

Figure 1. UVLO Operation

7.3.3 PWM Pin

The PWM pin incorporates an input tri-state function. The device forces the gate driver outputs to low when

PWM is driven into the tri-state window and the driver enters a low power state with zero exit latency. The pin

incorporates a weak pull-up to maintain the voltage within the tri-state window during low-power modes.

Operation into and out of tri-state mode follows the timing diagram outlined in Figure 2.

When VDD reaches the UVLO_H level, a tri-state voltage range (window) is set for the PWM input voltage. The

window is defined the PWM voltage range between PWM logic high (VIH) and logic low (VIL) thresholds. The

device sets high-level input voltage and low-level input voltage threshold levels to accommodate both 3.3 V

(typical) and 5 V (typical) PWM drive signals.

When the PWM exits tri-state, the driver enters CCM for a period of 4 µs, regardless of the state of the SKIP#

pin. Normal operation requires this time period in order for the auto-zero comparator to resume.

Figure 2. PWM Tri-State Timing Diagram

7.3.4 SKIP# Pin

The SKIP# pin incorporates the input tri-state buffer as PWM. The function is somewhat different. When SKIP# is

low, the zero crossing (ZX) detection comparator is enabled, and DCM mode operation occurs if the load current

is less than the critical current. When SKIP# is high, the ZX comparator disables, and the converter enters FCCM

mode. When both SKIP# and PWM are tri-stated, normal operation forces the gate driver outputs low and the

driver enters a low-power state. In the low-power state, the UVLO comparator remains off to reduce quiescent

current. When SKIP# is pulled low, the driver wakes up and is able to accept PWM pulses in less than 50 µs.

Copyright © 2015, Texas Instruments Incorporated

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