CSD97396Q4M

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SLPS572 – DECEMBER 2015

6.5 Electrical Characteristics

TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PLOSS

VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,

Power Loss(1)

1.9

W

ƒSW = 500 kHz, LOUT = 0.29 µH, TJ = 25°C

VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,

Power Loss(2)

2.2

W

ƒSW = 500 kHz, LOUT = 0.29 µH, TJ = 25°C

VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,

Power Loss(2)

2.6

W

ƒSW = 500 kHz, LOUT = 0.29 µH, TJ = 125°C

VIN

IQ

VIN quiescent current

PWM = Floating, VDD = 5 V, VIN= 24 V

1

µA

VDD

PWM = Float, SKIP# = VDD or 0 V

130

µA

IDD

Standby supply current

SKIP# = Float

8

µA

IDD

Operating supply current

PWM = 50% Duty cycle, ƒSW = 500 kHz

7.8

mA

POWER-ON RESET AND UNDERVOLTAGE LOCKOUT

VDD Rising

Power-on reset

4.15

V

VDD Falling

UVLO

3.7

V

Hysteresis

0.2

mV

PWM AND SKIP# I/O SPECIFICATIONS

Pull up to VDD

1700

RI

Input impedance

k

Ω

Pull down (to GND)

800

VIH

Logic level high

2.65

VIL

Logic level low

0.6

V

VIH

Hysteresis

0.2

VTS

Tri-state voltage

1.3

2

Tri-state activation time

tTHOLD(off1)

60

(falling) PWM(2)

ns

Tri-state activation time

tTHOLD(off2)

60

(rising) PWM(2)

Tri-state activation time

tTSKF

1

(falling) SKIP#(2)

µs

Tri-state activation time

tTSKR

1

(rising) SKIP# (2)

t3RD(PWM)

Tri-state exit time PWM(2)

100

ns

t3RD(SKIP#)

Tri-state exit time SKIP#(2)

50

µs

BOOTSTRAP SWITCH

VFBST

Forward voltage

IF = 10 mA

120

240

mV

IRLEAK

Reverse leakage(2)

VBST – VDD = 25 V

2

µA

(1)

Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.

(2)

Specified by design.

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