MPC8280 datasheet(256/1386 Pages) FREESCALE

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External Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

6-14

Freescale Semiconductor

IRQ7

INT_OUT

APE

Interrupt request 7—This input is one of the eight external lines that can request (by means of the

internal interrupt controller) a service routine from the core.

Interrupt output—This is an output driven from MPC8280’s internal interrupt controller. Assertion

of this output indicates that an unmasked interrupt is pending in MPC8280’s internal interrupt

controller.

Address parity error—This output pin is asserted when the MPC8280 detects wrong parity driven

on its address parity pins by an external master.

TRST

Test reset (JTAG)— Input only. This is the reset input to the MPC8280’s JTAG/COP controller. See

Section 13.1, “Overview,” and Section 13.6, “Nonscan Chain Operation.”

TCK

Test clock (JTAG)—Input only. Provides the clock input for MPC8280’s JTAG/COP controller.

TMS

Test mode select (JTAG)—Input only. Controls the state of MPC8280’s JTAG/COP controller.

TDI

Test data in (JTAG)—Input only. Data input to MPC8280’s JTAG/COP controller.

TDO

Test data out (JTAG)—Output only. Data output from MPC8280’s JTAG/COP controller.

TRIS

Three-state—Asserting TRIS forces all other MPC8280’s pins to high impedance state.

PORESET

PCI_RST

Power-on reset—When asserted, this input line causes the MPC8280 to enter power-on reset

state.

PCI reset—PCI reset input pin. When the MPC8280 is an agent in the PCI system, PCI_RST is

an input.

HRESET

Hard reset—This open drain line, when asserted causes the MPC8280 to enter hard reset state.

SRESET

Soft reset—This open drain line, when asserted causes the MPC8280 to enter the soft reset

state.

QREQ

Quiescent request— Output only. Indicates that MPC8280’s internal core is about to enter its low

power mode. In the MPC8280 this pin will be typically used for debug purposes.

RSTCONF

RSTCONF —Input used during reset configuration sequence of the chip. Find detailed

explanation of its function in Section 5.1.2, “Power-On Reset Flow,” and Section 5.4, “Reset

Configuration.”

MODCK1

AP[1]

TC[0]

BNKSEL[0]

MODCK1—Clock mode input. Defines the operating mode of internal clock circuits.

Address parity 1—(Input/output) The 60x master that drives the address bus, drives also the

address parity signals. The value driven on address parity 1 pin should give odd parity (odd

number of 1s) on the group of signals that includes address parity 1 and A[8–15].

Transfer Code 0—The transfer code output pins supply information that can be useful for debug

purposes for each of the MPC8280’s initiated bus transactions.

Bank Select 0—The bank select outputs are used for selecting SDRAM bank when the MPC8280

is in 60x compatible bus mode. BNKSEL0 is msb of the three BNKSEL signals.

Table 6-1. External Signals (continued)

Signal

Description

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