MPC8280 datasheet(255/1386 Pages) FREESCALE

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External Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

6-13

L_A28

PCI_RST

CORE_SRESET

Local bus address 28—Local bus address bit 28 output pin. In the local address bus bit 14 is most

significant and bit 31 is least significant.

PCI reset—PCI reset output pin. When the MPC8280 is the host in the PCI system, PCI_RST is

an output.

Core system reset—This is an input to the core. When this input pin is asserted the core branches

to its reset vector.

L_A29

PCI_INTA

Local bus address 29—Local bus address bit 29 output pin. In the local address bus bit 14 is most

significant and bit 31 is least significant.

PCI INTA—(output) When the MPC8280 is an agent of the PCI system, this pin is an output used

by the MPC8280 to signal an interrupt to the PCI host. (When the MPC8280 is the host in the PCI

system, the general IRQ pins are used for delivering PCI interrupts to the host.)

L_A30

PCI_REQ2

Local bus address 30—Local bus address bit 30 output pin. In the local address bus bit 14 is most

significant and bit 31 is least significant.

PCI arbiter request 2—PCI request 2 input pin. When the MPC8280’s internal PCI arbiter is used,

assertion of this pin indicates that an external PCI device is requesting the PCI bus.

L_A31

DLLOUT

Local bus address 31—Local bus address bit 31 output pin. In the local address bus bit 14 is most

significant and bit 31 is least significant.

DLL Clock Out—DLL output pin. This is the DLL output reference clock. See Figure 10-2 and

Figure 10-3.

LCL_D[0–31]

PCI_AD[31-0]

Local bus data—Local bus data input/output pins. In the local data bus bit 0 is most significant

and bit 31 is least significant.

PCI address/data—PCI bus address/data input/output pins. During an address phase

PCI_AD[31-0] contains a physical address, during a data phase PCI_AD[31-0] contains the data

bytes. In the PCI address/data bus, bit 31 is msb and bit 0 is lsb.

LCL_DP[0–3]

PCI_C/BE[3-0]

Local bus data parity—Local bus data parity input/output pins. In local bus write operations the

MPC8280 drives these pins. In local bus read operations the accessed device drives these pins.

LCL_DP[0] is driven with a value that gives odd parity with LCL_D[0–7]. LCL_DP[1] is driven with

a value that gives odd parity with LCL_D[8–15]. LCL_DP[2] is driven with a value that gives odd

parity with LCL_D[16–23]. LCL_DP[3] is driven with a value that gives odd parity with

LCL_D[24–31].

PCI command/byte enable—PCI command/byte enable input/output pins. The MPC8280 drives

these pins when it is the initiator of a PCI transfer. During an address phase the PCI_C/BE[3-0]

defines the command, during the data phase PCI_C/BE[3-0] defines the byte enables.

PCI_C/BE[3] is the msb and PCI_C/BE[0] is the lsb.

IRQ0

NMI_OUT

Interrupt request 0—This input is an external line that causes an MCP interrupt to the core.

Non-maskable interrupt output—This is an output driven from MPC8280’s internal interrupt

controller. Assertion of this output indicates that a non-maskable interrupt is pending in

MPC8280’s internal interrupt controller.

Table 6-1. External Signals (continued)

Signal

Description

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