AD9984APCBZ datasheet(25/44 Pages) AD

25 / 44 page

AD9984A

Rev. 0 | Page 25 of 44

Hex

Address

Read/Write,

Read Only

Bits

Default

Value

Description

*0** ****

Hsync Source Select. Determines the source of the Hsync for PLL and

sync processing. This bit is used only if Reg. 0x12, Bit 7 is set to 1 or if

both syncs are active.

0 = Hsync is from HSYNCx input pin.

1 = Hsync is from SOG.

**0* ****

Hsync Input Polarity Override.

0 = The chip selects the Hsync input polarity.

1 = The input polarity of Hsync is controlled by Reg. 0x12, Bit 4.

***1 ****

Hsync Input Polarity. This bit is used only if Reg. 0x12, Bit 5 is set to 1.

0 = Hsync input polarity is negative.

1 = Hsync input polarity is positive.

**** 1***

Hsync Output Polarity. Sets the polarity of the Hsync output signal

(HSOUT).

0 = HSOUT polarity is negative.

1 = HSOUT polarity is positive.

0x13

R/W

7:0

0010 0000

Hsync Duration

Sets the number of pixel clocks that HSOUT is active.

0x14

R/W

0*** ****

Vsync Control

Vsync Source Override.

0 = The chip determines the active Vsync source.

1 = The active Vsync source is set by Reg. 0x14, Bit 6.

*0** ****

Vsync Source Select. Determines the source of Vsync for sync

processing. This bit is used only if Reg. 0x14, Bit 7 is set to 1.

0 = Vsync is from the VSYNCx input pin.

1 = Vsync is from the sync separator.

**0* ****

Vsync Input Polarity Override.

0 = The chip selects Vsync input polarity.

1 = The input polarity of Vsync is set by Reg. 0x14, Bit 4.

***1 ****

Vsync Input Polarity. This bit is used only if Reg. 0x14, Bit 5 is set to 1.

0 = Vsync input polarity is negative.

1 = Vsync input polarity is positive.

**** 1***

Vsync Output Polarity. Sets the polarity of the output Vsync signal

(VSOUT).

0 = VSOUT polarity is negative.

1 = VSOUT polarity is positive.

**** *0**

Vsync Filter Enable. This needs to be enabled when using the Hsync

to Vsync counter.

0 = The Vsync filter is disabled.

1 = The Vsync filter is enabled.

**** **0*

Vsync Duration Block Enable. This is designed to be used with the

Vsync filter.

0 = Vsync output duration is unchanged.

1 = Vsync output duration is set by Register 0x15.

0x15

R/W

7:0

0000 1010

Vsync Duration

Sets the number of Hsyncs that Vsync out is active. This is only used if

Reg. 0x14, Bit 1 is set to 1.

0x16

R/W

7:0

0000 0000

Precoast

The number of Hsync periods to coast prior to Vsync.

0x17

R/W

7:0

0000 0000

Postcoast

The number of Hsync periods to coast after Vsync.

0x18

R/W

0*** ****

Coast and Clamp

Control

Coast Source. Determines the source of the coast signal.

0 = Using internal coast generated from Vsync.

1 = Using external coast signal from COAST pin.

*0** ****

Coast Polarity Override.

0 = The chip selects the coast polarity.

1 = The polarity of the coast signal is set by Reg. 0x18, Bit 5.

**1* ****

Coast Polarity. This bit is used only if Reg. 0x18, Bit 6 is set to 1.

0 = Coast polarity is negative.

1 = Coast polarity is positive.

***0 ****

Clamp Source Select. Determines the source of the clamp timing.

0 = Uses the internal clamp generated from Hsync.

1 = Uses the external CLAMP signal.

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