AD9984APCBZ datasheet(32/44 Pages) AD

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AD9984A

Rev. 0 | Page 32 of 44

0x12—Bit[5] Hsync Input Polarity Override

This bit determines whether the chip selects the Hsync input

polarity or if it is specified. Setting this bit to 0 allows the chip

to automatically select the polarity of the input Hsync. Setting it

to 1 indicates that Bit 4 of Register 0x12 specifies the polarity.

Power-up default is 0.

Table 20. Hsync Input Polarity Override Bit

Value

Result

Hsync polarity determined by chip.

Hsync polarity determined by user (Register 0x12, Bit 4).

0x12—Bit[4] Hsync Input Polarity

If Bit 5 of Register 0x12 is 1, the value of this bit specifies the

polarity of the input Hsync. Setting this bit to 0 indicates a

negative Hsync input polarity. Setting this bit to 1 indicates a

positive Hsync input polarity. Power-up default is 1.

Table 21. Hsync Input Polarity Bit

Value

Result

Hsync input polarity is negative.

Hsync input polarity is positive.

0x12—Bit[3] Hsync Output Polarity

This bit sets the polarity of the Hsync output (HSOUT). Setting

this bit to 0 indicates a negative HSOUT polarity. Setting this bit

to 1 indicates a positive HSOUT polarity.

Table 22. Hsync Output Polarity Bit

Value

Result

HSOUT polarity is negative.

HSOUT polarity is positive.

0x13—Bits[7:0] Hsync Duration

This 8-bit register sets the duration of the HSOUT pulse. The

leading edge of the Hsync output is triggered by the internally

generated, phase-adjusted, PLL feedback clock. The AD9984A

then counts a number of pixel clocks equal to the value in this

phase-adjusted.

VSYNC CONTROL

0x14—Bit[7] Vsync Source Override

This bit is the active Vsync override. Setting this to 0 allows the

chip to determine the active Vsync source, setting it to 1 uses

Bit 6 of Register 0x14 to determine the active Vsync source.

Power-up default value is 0.

Table 23. Vsync Source Override Bit

Value

Result

Vsync source determined by chip.

Vsync source determined by user (Register 0x14, Bit 6).

0x14—Bit[6] Vsync Source Select

This bit selects the source of the Vsync for sync processing only

if Bit 7 of Register 0x14 is set to 1. Setting Bit 6 to 0 specifies the

Vsync from the input pin. Setting it to 1 selects Vsync from the

sync separator. Power-up default is 0.

Table 24. Vsync Source Select Bit

Value

Result

Vsync from VSYNCx input pin.

Vsync from sync separator.

0x14—Bit[5] Vsync Input Polarity Override

This bit sets whether the chip selects the Vsync input polarity or

if it is specified. Setting this bit to 0 allows the chip to

automatically select the polarity of the input Vsync. Setting this

bit to 1 indicates that Bit 4 of Register 0x14 specifies the

polarity. Power-up default is 0.

Table 25. Vsync Input Polarity Override Bit

Value

Result

Vsync polarity determined by chip.

Vsync polarity determined by user (Register 0x14, Bit 4).

0x14—Bit[4] Vsync Input Polarity

If Bit 5 of Register 0x14 is 1, the value of this bit specifies the

polarity of the input Vsync. Setting this bit to 0 indicates a

negative Vsync input polarity. Setting this bit to 1 indicates a

positive Vsync input polarity. Power-up default is 1.

Table 26. Vsync Input Polarity Bit

Value

Result

Vsync input polarity is negative.

Vsync input polarity is positive.

0x14—Bit[3] Vsync Output Polarity

This bit sets the polarity of the Vsync output (VSOUT). Setting

this bit to 0 indicates a negative VSOUT polarity. Setting this bit

to 1 indicates a positive VSOUT polarity. Power-up default is 1.

Table 27. Vsync Output Polarity Bit

Value

Result

VSOUT polarity is negative.

VSOUT polarity is positive.

0x14—Bit[2] Vsync Filter Enable

This bit enables the Vsync filter allowing precise placement of

the Vsync with respect to the Hsync and facilitating the correct

operation of the Hsyncs/Vsync count.

Table 28. Vsync Filter Enable Bit

Value

Result

Vsync filter disabled.

Vsync filter enabled.

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