AD9984APCBZ datasheet(14/44 Pages) AD

14 / 44 page

AD9984A

Rev. 0 | Page 14 of 44

CLOCK GENERATION

A PLL is used to generate the pixel clock. The Hsync input

provides a reference frequency to the PLL. A voltage controlled

oscillator (VCO) generates a much higher pixel clock frequency.

The pixel clock is divided by the PLL divide value (Register 0x01

and Register 0x02) and phase-compared with the Hsync input.

Any error is used to shift the VCO frequency and maintain lock

between the two signals.

The stability of this clock is a very important element in provid-

ing the clearest and most stable image. During each pixel time,

the signal slews from the old pixel amplitude and settles at its

new value; this is called the slewing time. Then, the input voltage

stabilizes before the signal must slew to a new value; this is called

the stable time. The ratio of the slewing time to the stable time is

a function of the graphics DAC bandwidth and the bandwidth

of the transmission system (cable and termination). This ratio is

also a function of the overall pixel rate. If the dynamic charac-

teristics of the system remain fixed, the slewing and settling

time is likewise fixed. This time must be subtracted from the

total pixel period, leaving the stable period. At higher pixel

frequencies, the total cycle time is shorter and the stable pixel

time becomes shorter as well.

PIXEL CLOCK

INVALID SAMPLE TIMES

Figure 7. Pixel Sampling Times

Any jitter in the clock reduces the precision of the sampling

time and it must also be subtracted from the stable pixel time.

Considerable care has been taken in the design of the AD9984A

clock generation circuit to minimize jitter. The clock jitter of the

AD9984A is low in all operating modes, making the reduction

in the valid sampling time due to jitter negligible.

The PLL characteristics are determined by the loop filter design,

the PLL charge pump current, and the VCO range setting. The

loop filter design is illustrated in Figure 8. Recommended settings

of the VCO range and charge pump current for VESA standard

display modes are listed in Table 10.

8.2nF

82nF

1.5kΩ

FILT

PVD

Figure 8. PLL Loop Filter Design

Four programmable registers are provided to optimize the

performance of the PLL. These registers are the 12-bit divisor

current register, and the 5-bit phase adjust register.

The 12-Bit Divisor Register

The input Hsync frequencies can accommodate any Hsync as

long as the product of the Hsync and the PLL divisor falls

within the operating range of the VCO. The PLL multiplies the

frequency of the Hsync signal, producing pixel clock frequencies

in the range of 10 MHz to 170 MHz. The divisor register controls

the exact multiplication factor. This register can be set to any

value between 2 and 4095 as long as the output frequency is

within range.

The 2-Bit VCO Range Register

To improve the noise performance of the AD9984A, the VCO

operating frequency range is divided into four overlapping

regions. The VCO range register sets this operating range. The

frequency ranges for the four regions are shown in Table 8.

Table 8. VCO Frequency Ranges

PV1

PV0

Pixel Clock Range (MHz)

KVCO Gain (MHz/V)

10 to 311

150

31 to 62

150

62 to 124

150

124 to 170

150

1 For frequencies of 18 MHz or lower, enable the VCO low range bit (Reg. 0x36[0]).

The 3-Bit Charge Pump Current Register

This register varies the current that drives the low-pass loop

filter. The possible current values are listed in Table 9.

Table 9. Charge Pump Current/Control Bits

Ip2

Ip1

Ip0

Current (μA)

100

150

250

350

500

750

1500

The 5-Bit Phase Adjust Register

The phase of the generated sampling clock can be shifted to

locate an optimum sampling point within a clock cycle. The

phase adjust register provides 32 phase-shift steps of 11.25°

each. The Hsync signal with an identical phase shift is available

through the HSOUT pin. Phase adjust is still available if an

external pixel clock is used. The COAST pin or the internal

coast is used to allow the PLL to continue to run at the same

frequency in the absence of the incoming Hsync signal or

during disturbances in Hsync (such as from equalization

pulses). This can be used during the vertical sync period or at

any other time that the Hsync signal is unavailable.

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