AD9984A

Rev. 0 | Page 19 of 44

POWER MANAGEMENT

To meet display requirements for low standby power, the

AD9984A includes a power-down mode. The power-down state

can be controlled manually (via Pin 17 or Register 0x1E, Bit 3),

or automatically by the chip. If automatic control is selected

(Register 0x1E, Bit 4 =1), the AD9984A’s decision is based on

the status of the following sync detect bits in Register 0x24: Bit 2,

Bit 3, Bit 6, and Bit 7. If either an Hsync or a sync-on-green input

is detected on any input, the chip powers up; otherwise, it powers

down. For manual control, the AD9984A allows flexibility of

control through both a dedicated pin and a register bit. For the

dedicated pin, a hardware watchdog circuit controls power-down,

while software controls power-down for the register bit. With

manual power-down control, the polarity of the power-down

pin must be set (Register 0x1E, Bit 2) whether the pin is used or

not. If unused, it is recommended to set the polarity to active

high and hardwire the pin to ground with a 10 kΩ resistor.

In power-down mode, several circuits continue to operate

normally. The serial register and sync detect circuits maintain

power so that the AD9984A can be woken up from its power-

down state. The band gap circuit maintains power because it is

needed for sync detection. The sync-on-green and SOGOUT

functions continue to operate because SOGOUT is needed

when sync detection is performed by a secondary chip. All of

these circuits require minimal power to operate. Typical

standby power on the AD9984A is about 50 mW.

There are two options that can be selected when in power-

down. These are controlled by Bit 0 and Bit 1 in Register 0x1E.

Bit 0 controls whether the SOGOUT pin is in high impedance

or not. In most cases, the user does not place SOGOUT in high

impedance during normal operation. The option to put SOGOUT

in high impedance is included mainly to allow for factory testing

modes. Bit 1 keeps the AD9984A powered up while placing

only the outputs in high impedance. This option is useful when

the data outputs from two chips are connected on a PCB and

the user wants to switch instantaneously between the two.

Table 11.Power-Down Control and Mode Descriptions

Inputs

Mode

Auto Power-Down Control1

Power-Down2

Sync Detect3

Powered on/Comments

Power-Up

1

X

1

Everything.

Power-Down

1

X

0

Only the serial bus, sync activity detect,

SOG, band gap reference.

Power-Up

0

0

X

Everything.

Power-Down

0

1

X

Only the serial bus, sync activity detect,

SOG, band gap reference.

TIMING DIAGRAMS

The timing diagrams in Figure 14 to Figure 17 show the operation of the AD9984A. The output data clock signal is created so that its

rising edge always occurs between data transitions and can be used to latch the output data externally. There is a pipeline in the AD9984A

that must be flushed before valid data becomes available. This means six data sets are present before valid data is available.

DATACK

DATA

HSOUT

Figure 14. Output Timing