AD9984APCBZ datasheet(38/44 Pages) AD

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AD9984A

Rev. 0 | Page 38 of 44

0x25—Bit[6] HSYNC1 Polarity

This bit indicates the polarity of HSYNC1 input.

Table 71. HSYNC1 Polarity Bit

Value

Result

HSYNC1 polarity is negative.

HSYNC1 polarity is positive.

0x25—Bit[5] VSYNC0 Polarity

This bit indicates the polarity of VSYNC0 input.

Table 72. VSYNC0 Polarity Bit

Value

Result

VSYNC0 polarity is negative.

VSYNC0 polarity is positive.

0x25—Bit[4] VSYNC1 Polarity

This bit indicates the polarity of VSYNC1 input.

Table 73. VSYNC1 Polarity Bit

Value

Result

VSYNC1 polarity is negative.

VSYNC1 polarity is positive.

0x25—Bit[3] COAST Polarity

This bit indicates the polarity of the external COAST signal.

Table 74. COAST Polarity Bit

Value

Result

COAST polarity is negative.

COAST polarity is positive.

0x25—Bit[2] CLAMP Polarity

This bit indicates the polarity of the CLAMP signal.

Table 75. CLAMP Polarity Bit

Value

Result

CLAMP polarity is negative.

CLAMP polarity is positive.

0x25—Bit[1] Extraneous Pulse Detection

A second output from the Hsync filter, this status bit tells

whether extraneous pulses are present on the incoming sync

signal. Often, extraneous pulses are used for copy protection, so

this status bit can be used for this purpose.

Table 76. Extraneous Pulse Detection Bit

Value

Result

No extraneous pulses detected during active Hsync.

Extraneous pulses detected during active Hsync.

0x25—Bit[0] Sync Filter Lock

When this bit is set to 1, the sync filter is locked. When set to 0,

the sync filer is unlocked.

HSYNC COUNT

0x26—Bits[7:0] Hsyncs per Vsync MSBs

This register contains the 8 MSBs of the 12-bit counter that

reports the number of Hsyncs per Vsync on the active input. It

is useful for determining the mode and is an aid in setting the

PLL divide ratio.

0x27—Bits[7:4] Hsyncs per Vsync LSBs

This register contains the four LSBs of the 12-bit counter that

reports the number of Hsyncs per Vsync on the active input.

TEST REGISTERS

0x28—Bits[7:0] Test Register 1

Must be written to 0xBF for proper operation.

0x29—Bits[7:0] Test Register 2

Must be written to 0x02 for proper operation.

0x2A—Bits[7:0] Test Register 3

Read only bits for future use.

0x2B—Bits[7:0] Test Register 4

Read only bits for future use.

0x2C—Bits[7:5] Offset Hold

Must be written to default 0x00 for proper operation.

0x2C—Bit[4] Auto-Offset Hold

This bit controls whether the auto-offset function runs

continuously or only once and holds the result. Continuous

updates are recommended because they allow the AD9984A to

compensate for drift over time, temperature, and so on. If one-

time updates are preferred, they should be performed every

time the part is powered up and when there is a mode change.

To perform a one-time update, auto-offset must first be enabled

(Register 0x1B, Bit 5). Next, this bit (auto-offset hold) must first

be set to 0 to let the auto-offset function operate and settle to a

final value. Auto-offset hold should then be set to 1 to hold the

offset values that the auto circuitry calculates. The AD9984A

auto-offset circuit’s maximum settle time is 10 updates. For

example, if the update frequency is set to once every 192 Hsyncs,

the maximum settling time is 1920 Hsyncs (10 × 192 Hsyncs).

Table 77. Auto-Offset Hold Bit

Value

Result

Allows auto-offset to continuously update.

Disables auto-offset updates and holds the current

auto-offset values.

0x2C—Bits[3:0]

Must be written to 0x0 for proper operation.

0x2D—Bits[7:0] Test Register 5

Read/write bits for future use. Must be written to 0xE8 for

proper operation.

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