AD9984APCBZ datasheet(35/44 Pages) AD

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AD9984A

Rev. 0 | Page 35 of 44

INPUT AND POWER CONTROL

0x1E—Bit[7] Channel Select Override

This bit provides an override to the automatic input channel

selection. Power-up default setting is 0.

Table 43. Channel Select Override Bit

Value

Result

Channel input source determined by chip.

Channel input source determined by user,

(Register 0x1E, Bit 6).

0x1E—Bit[6] Channel Select

This bit selects the active input channel if Bit 7 of Register 0x1E

is 1. This selects between Channel 0 data and syncs or Channel 1

data and syncs. Power-up default setting is 0.

Table 44. Channel Select Bit

Value

Result

Channel 0 data and syncs are selected.

Channel 1 data and syncs are selected.

0x1E—Bit[5] Programmable Bandwidth

This bit selects between a low or high input bandwidth; having

a low input bandwidth is useful in limiting noise for lower

frequency inputs. The power-up default setting is 1. Low analog

input bandwidth is ~7 MHz; high analog input bandwidth is

~300 MHz.

Table 45. Programmable Bandwidth Bit

Value

Result

Low analog input bandwidth.

High analog input bandwidth.

0x1E—Bit[4] Power-Down Control Select

This bit determines whether power-down is controlled manually or

automatically by the chip. If automatic control is selected (by

setting this bit to 1), the AD9984A’s decision is based on the

status of the some of the sync detect bits (Register 0x24, Bit 2,

Bit 3, Bit 6, and Bit 7). If either an Hsync or a sync-on-green

input is detected on any input, the chip powers up or powers

down. For manual control, the AD9984A allows the flexibility

of control through both a dedicated pin and a register bit. The

dedicated pin allows a hardware watchdog circuit to control

power-down, whereas the register bit allows power-down to be

controlled by software. With manual power-down control, the

polarity of the power-down pin must be set (Register 0x1E, Bit 2)

whether it is used or not. If unused, it is recommended to set

the polarity to active high and hardwire the pin to ground with a

10 kΩ resistor.

Table 46. Power-Down Control Select Bit

Value

Result

Manual power-down control (user determines

power-down).

Auto power-down control (chip determines

power-down).

0x1E—Bit[3] Power-Down

This bit is used to manually place the chip in power-down

mode. It is only used if manual power-down control is selected

(Register 0x1E, Bit 4 = 0). Both the state of this register bit

and the power-down pin (Pin 17) are used to control manual

power-down. (See the Power Management section for more

details on power-down.)

Table 47. Power-Down Bit

Value

Pin 17

Result

Normal operation.

Power-down.

0x1E—Bit[2] Power-Down Pin Polarity

This bit defines the polarity of the power-down pin (Pin 17).

It is only used if manual power-down control is selected

(Register 0x1E, Bit 4 = 0).

Table 48. Power-Down Pin Polarity Bit

Value

Result

PWRDN polarity is negative.

PWRDN polarity is positive.

0x1E—Bit[1] Power-Down Fast Switching Control

This bit controls a special fast switching mode. With this bit, the

AD9984A can stay active during power-down and only puts the

outputs in high impedance. This option is useful when the data

outputs from two chips are connected on a PCB and the user

wants to instantaneously switch between the two.

Table 49. Power-Down Fast Switching Control Bit

Value

Result

Normal power-down operation.

The chip stays powered up, and the outputs are put

in high impedance mode.

0x1E—Bit[0] SOGOUT High Impedance Control

This bit controls whether or not the SOGOUT output pin is in

high impedance when in power-down mode. In most cases,

SOGOUT is not put in high impedance during normal operation

because it is usually needed for sync detection by the graphics

controller. The option to put SOGOUT in high impedance is

included mainly to allow for factory testing modes.

Table 50. SOGOUT High Impedance Control Bit

Value

Result

The SOGOUT operates as normal during power-down.

The SOGOUT is in high impedance during

power-down.

OUTPUT CONTROL

0x1F—Bits[7:5] Output Mode

These bits choose between three options for the output mode.

In 4:4:4 mode, RGB is standard. In 4:2:2 mode, YCbCr is standard,

which reduces the number of output pins from 30 to 20. In 4:4:4

DDR output mode, the data is in RGB mode, but changes on

every clock edge. The power-up default setting is 100.

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