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CS4525 датащи(PDF) 23 Page - Cirrus Logic

номер детали CS4525
подробное описание детали  30 W Digital Audio Amplifier with Integrated ADC
PDF  98 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4525 датащи(HTML) 23 Page - Cirrus Logic

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CS4525
XTI SWITCHING SPECIFICATIONS
Notes:
15. See “Clock Frequency (ClkFreq[1:0])” on page 69.
SYS_CLK SWITCHING SPECIFICATIONS
AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; Input: Logic 0 = DGND; Logic 1 = VD, SYS_CLK Output:
CL =20pF.
PWM_SIGX SWITCHING SPECIFICATIONS
AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; Load = 10 pF.
Parameter
Symbol
Min
Typ
Max
Unit
External Crystal Operating Frequency
ClkFreq[1:0] = ‘00’
(Note 15)
ClkFreq[1:0] = ‘01’
ClkFreq[1:0] = ‘10’
FCLK
18.240
24.330
26.730
18.432
24.576
27.000
18.617
24.822
27.270
MHz
MHz
MHz
XTI Duty Cycle
45
50
55
%
Parameter
Symbol
Min
Typ
Max
Unit
External Clock Operating Frequency
ClkFreq[1:0] = ‘00’
(Note 15)
ClkFreq[1:0] = ‘01’
ClkFreq[1:0] = ‘10’
FCLK
18.240
24.330
26.730
18.432
24.576
27.000
18.617
24.822
27.270
MHz
MHz
MHz
Rising Edge RST to start of SYS_CLK
tsclko
-
1024*tsclki
-
SYS_CLK Period
tsclki
37.04
-
54.25
ns
SYS_CLK Duty Cycle
45
50
55
%
SYS_CLK high time
tclkih
16.67
-
29.84
ns
SYS_CLK low time
tclkil
16.67
-
29.84
ns
Parameter
Symbol
Min
Typ
Max
Unit
Rise Time of PWM_SIGx
tr
-2.1
-
ns
Fall Time of PWM_SIGx
tf
-1.4
-
ns
SYS_CLK
___
RST
(output)
tsclko
Figure 9. SYS_CLK Timing from Reset
PWM_SIGx
tr
tf
Figure 10. PWM_SIGX Timing



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