CS4525 datasheet(71/98 Pages) CIRRUS

71 / 98 page

DS726PP1

CS4525

9.2

Input Configuration (Address 02h)

9.2.1

Input Source Selection (ADC/SP)

Default = 0

Function:

This bit selects the audio input source.

9.2.2

ADC High-Pass Filter Enable (EnAnHPF)

Default = 1

Function:

Controls the operation of the ADC high-pass filter.

9.2.3

Serial Port Sample Rate (SPRate[1:0]) - Read Only

Function:

Identifies the sample rate of the incoming LRCK signal on the serial audio input port based on the setting

of the ClkFreq[1:0] bits in Register 01h, the frequency of the internal system clock, and the frequency of

the input LRCK signal.

9.2.4

Input Serial Port Digital Interface Format (DIF [2:0])

Default = 000

Function:

Selects the serial audio interface format used for the data in on SDIN. The required relationship between

the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options

are detailed in the section “Serial Audio Interfaces” on page 62.

432

ADC/SP

EnAnHPF

Reserved

SPRate1

SPRate0

DIF2

DIF1

DIF0

ADC/SP Setting

Audio Input Source

0 ..........................................Digital input from the serial audio input port.

1 ..........................................Analog input from the internal ADC.

EnAnHPF Setting

ADC High-Pass Filter State

0 ..........................................ADC high-pass filter disabled.

1 ..........................................ADC high-pass filter enabled.

SPRate[1:0] Setting

Identified Input Sample Rate

00 ........................................32 kHz

01 ........................................44.1 kHz

10 ........................................48 kHz

11.........................................96 kHz

DIF[2:0] Setting

Input Serial Port Serial Audio Interface Format

000 ......................................Left-Justified, up to 24-bit data.

001 ......................................I²S, up to 24-bit data.

010 ......................................Right-Justified, 24-bit data.

011.......................................Right-Justified, 20-bit data.

100 ......................................Right-Justified, 18-bit data.

101 ......................................Right-Justified, 16-bit data.

110.......................................Reserved.

111 .......................................Reserved.

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