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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS4525 датащи(PDF) 22 Page - Cirrus Logic |
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CS4525 датащи(HTML) 22 Page - Cirrus Logic |
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22 / 98 page  22 DS726PP1 CS4525 AUX SERIAL AUDIO I/O PORT SWITCHING SPECIFICATIONS AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; AUX_SDOUT & DLY_SDOUT CL = 15 pF; Inputs: Logic 0 = DGND; Logic 1 = VD; (Note 11). Notes: 11. FCLK is the frequency of the crystal connected to the XTI/XTO pins or the input SYS_CLK signal. TCLK =1/FCLK. 12. FSI is the frequency of the input LRCK signal. TSI =1/FSI 13. May vary during normal operation. 14. FSCLKI is the frequency of the input SCLK signal. TSCLKI =1/FSCLKI. Parameters Symbol Min Typ Max Units Input Source: Analog Inputs (Internal ADC) Output Sample Rate ClkFreq[1:0] = ‘00’ ClkFreq[1:0] = ‘01’ ClkFreq[1:0] = ‘10’ FSO - - - FCLK/384 FCLK/512 FCLK/512 - - - Hz Hz Hz AUX_LRCK Duty Cycle - 50 - % AUX_LRCK Period - 1/FSO -s AUX_SCLK Frequency ClkFreq[1:0] = ‘00’ ClkFreq[1:0] = ‘01’ ClkFreq[1:0] = ‘10’ FSCLKO - - - 48*FSO 64*FSO 64*FSO - - - Hz Hz Hz AUX_SCLK Duty Cycle - 50 - % AUX_SCLK Period - 1/FSCLKO -s Input Source: Serial Audio Input Port Output Sample Rate FS-In = 32kHz, 44.1 kHz, 48 kHz FS-In =96 kHz FSO - - FSI FSI/2 - - Hz Hz AUX_LRCK Duty Cycle (Note 13) 45 - 55 % AUX_LRCK Period (Note 12, 13)TSI - TCLK TSI TSI + TCLK s AUX_SCLK Frequency FS-In = 32kHz, 44.1 kHz, 48 kHz (Note 14) FS-In =96 kHz - - FSCLKI FSCLKI/2 - - Hz Hz AUX_SCLK Duty Cycle 30 - 70 % AUX_SCLK Period FS-In = 32kHz, 44.1 kHz, 48 kHz (Note 13, 14)FS-In =96 kHz TSCLKI - TCLK 2*TSCLKI - TCLK TSCLKI 2*TSCLKI TSCLKI + TCLK 2*TSCLKI + TCLK s s Input Source: Analog Inputs or Serial Audio Input Port AUX_LRCK Rising Edge to AUX_SCLK Falling Edge tLTSF - - 20 ns AUX_SCLK Rising Edge to Data Output Valid tSRDV -- TCLK + 20 ns DLY_SDIN Setup Time Before AUX_SCLK Rising Edge tDIS 25 - - ns DLY_SDIN Hold Time After AUX_SCLK Rising Edge tDIH 10 - - ns AUX_LRCK AUX_SCLK AUX_SDOUT DLY_SDOUT DLY_SDIN MSB MSB MSB - 1 MSB - 1 LSB LSB tLTSF tSRDV tDISU tDIH Figure 8. AUX Serial Port Interface Master Mode Timing |
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