CS4525 datasheet(69/98 Pages) CIRRUS

69 / 98 page

DS726PP1

CS4525

9. REGISTER DESCRIPTIONS

All registers are read/write unless otherwise stated. All “Reserved” bits must maintain their default state.

9.1

Clock Configuration (Address 01h)

9.1.1

SYS_CLK Output Enable (EnSysClk)

Default = 1

Function:

This bit controls the output driver for the SYS_CLK signal. When cleared, the output driver is disabled and

the SYS_CLK pin is high-impedance. When set, the output driver is enabled.

If the SYS_CLK output is unused, this bit should be set to ‘0’b to disable the driver.

9.1.2

SYS_CLK Output Divider (DivSysClk)

Default = 0

Function:

This bit determines the divider for the XTAL clock signal for generating the SYS_CLK signal.

This divider is only available if the clock source is an external crystal attached to XTI/XTO and the

SYS_CLK output is enabled.

9.1.3

Clock Frequency (ClkFreq[1:0])

Default = 01

Function:

These bits must be set to identify the nominal clock frequency of the crystal attached to the XTI/XTO pins

or that of the input SYS_CLK signal. See the XTI Switching Specifications table on page 23 and the

SYS_CLK Switching Specifications table on page 23 for complete input frequency range specifications.

76543210

EnSysClk

DivSysClk

ClkFreq1

ClkFreq0

HP/MutePol

HP/Mute

PhaseShift

FreqShift

EnSysClk Setting

Output Driver State

0 ..........................................Output driver disabled.

1 ..........................................Output driver enabled.

DivSysClk Setting

SYS_CLK Output Frequency

0 ..........................................FSYS_CLK =FXTAL

1 ..........................................FSYS_CLK =FXTAL/2

ClkFreq[1:0] Setting

Specified Nominal Input Clock Frequency

00 ........................................18.432 MHz

01 ........................................24.576 MHz

10 ........................................27.000 MHz

11.........................................Reserved

CS4525 датащи(PDF) 69 Page - Cirrus Logic

CS4525 датащи(HTML) 69 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

датащи скачать

ссылки URL