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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9915/PCBZ датащи(PDF) 50 Page - Analog Devices |
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AD9915/PCBZ датащи(HTML) 50 Page - Analog Devices |
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50 / 51 page  Data Sheet AD9915 REGISTER MAP AND BIT DESCRIPTIONS analog.com Rev. G | 50 of 51 Table 30. Bit Descriptions for Profile 0 to Profile 7 Phase Offset and Amplitude Registers Bit(s) Mnemonic Description [27:16] Amplitude scale factor This 12-bit word controls the DDS amplitude. Note that the OSK enable bit (0x00[8]) must be set to logic high to make amplitude adjustments. [15:0] Phase offset word This 16-bit word controls the DDS phase offset. USR0 Register—Address 0x1B Table 31. Bit Descriptions for USR0 Register Bit(s) Mnemonic Description [31:25] Open 24 PLL lock This is a readback bit only. If Logic 1 is read back, the PLL is locked. Logic 0 represents a nonlocked state. [23:8] (See description) These bits must always be programmed with the default values listed in the default column in Table 17. 7 Reserved Must be kept at Logic 0 (default). 6 CAL with SYNC 0 = a SYNC_IN signal is not required to calibrate the DAC clock. 1 = a SYNC_IN signal is required to calibrate the DAC clock. [5:3] SYNC_OUT delay ADJ Provides the ability to delay the SYNC_OUT signal for multichip synchronization purposes. [2:0] SYNC_IN delay ADJ Provides the ability to delay the internal SYNC_IN signal for multichip synchronization purposes. |
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