AD9915SLASHPCBZ datasheet(28/51 Pages) AD

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Data Sheet

AD9915

FUNCTIONAL BLOCK DETAIL

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Rev. G | 28 of 51

status of the DROVER pin is also shown with the assumption that

the DRG over output enable bit has been set.

The circled numbers in Figure 39 indicate specific events, which are

explained as follows:

Event 1—Indicates the instant that an input/output update registers

that the digital ramp enable bit is set.

Event 2—DRCTL transitions to Logic 1, initiating a positive slope at

the DRG output.

Event 3—DRCTL transitions to Logic 0, which has no effect on the

DRG output.

Event 4—Because the digital ramp no-dwell high bit is set, the

moment that the DRG output reaches the upper limit, it immediately

switches to the lower limit, where it remains until the next Logic 0 to

Logic 1 transition of DRCTL.

Event 5—DRCTL transitions from Logic 0 to Logic 1, which restarts

a positive slope ramp.

Event 6 and Event 7—DRCTL transitions are ignored until the DRG

output reaches the programmed upper limit.

Event 8—Because the digital ramp no-dwell high bit is set, the

moment that the DRG output reaches the upper limit, it immediately

switches to the lower limit, where it remains until the next Logic 0 to

Logic 1 transition of DRCTL.

Operation with the digital ramp no-dwell low bit set (instead of the

digital ramp no-dwell high bit) is similar, except that the DRG output

ramps in the negative direction on a Logic 1 to Logic 0 transition of

DRCTL and jumps to the upper limit upon reaching the lower limit.

Figure 39. No-Dwell High Ramp Generation

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