AD9915SLASHPCBZ datasheet(29/51 Pages) AD

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Data Sheet

AD9915

FUNCTIONAL BLOCK DETAIL

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Rev. G | 29 of 51

DROVER Pin

The DROVER pin provides an external signal to indicate the sweep

status of the DRG (assuming the DRG is enabled via CFR2[19] = 1

and the DROVER pin is enabled via CFR2[13] = 1). The behavior

of the DROVER pin depends on the state of the no-dwell bits

(CFR2[17:18]).

With neither no-dwell bit set (dwell operation), the DROVER pin is

Logic 1 whenever the DRG output is at the upper or lower limit

(per the prevailing sweep direction). Upon initiation of a new sweep,

the DROVER pin switches to Logic 0 until the DRG output again

reaches the appropriate limit.

With either (but not both) no-dwell bit set (no-dwell operation), the

DROVER pin behavior is the same as for dwell operation. However,

the DROVER pin remains Logic 1 even after the DRG returns to the

starting point as prescribed by no-dwell operation. Upon initiation of

a new sweep, the DROVER pin switches to Logic 0 until the DRG

output again reaches the appropriate limit.

With both no-dwell bits set (bidirectional sweep operation), instead

of providing a static indication, the DROVER pin generates a

positive pulse for two SYNC_CLK clock cycles on the final step the

DRG makes to reach either of the programmed limits. That is, a

positive pulse is generated each time the DRG output reaches the

upper limit and a positive pulse each time the DRG output reaches

the lower limit.

Frequency Jumping Capability in DRG Mode

Another feature of the AD9915 allows the user to skip a predefined

range of frequencies during a normal sweep. The frequency jump

enable bit in CFR2 (0x01[14]) enables this functionality. When this

bit is set, the sweeping logic monitors the instantaneous frequency.

For example, during an up sweep, when the sweeping logic detects

that the next output of the DRG sweep accumulator will equal or

exceed the frequency point defined in the lower frequency jump

normal sweeping), the output of the DRG sweep accumulator skips

directly to the frequency value set in the upper frequency jump

frequency vs. time profile depicting an example of the behavior of

the frequency jump feature.

A second frequency jump can also be allowed if the frequency jump

registers are reprogrammed before the sweeping is complete.

The following rules apply when this feature is enabled:

►

The frequency jump feature requires that P and N (see the DRG

Slope Control section) be greater than 2.

►

The frequency jump values must lie between the lower limit and

upper limit of the frequency sweep range.

►

The value stored in the lower frequency jump register must be

less than the value stored in the upper frequency jump register.

►

Setting both no-dwell bits (0x01[18:17]) to Logic 1 disables the

frequency jump feature.

Figure 40. Frequency vs. Time

POWER-DOWN CONTROL

The AD9915 offers the ability to independently power down three

specific sections of the device. Power-down functionality applies to

the following:

►

Digital core

►

DAC

►

Input REF CLK clock circuitry

A power-down of the digital core disables the ability to update the

serial/parallel input/output port. However, the digital power-down

bit (0x00[7]) can still be cleared to prevent the possibility of a

nonrecoverable state.

Software power-down is controlled via three independent pow-

er-down bits in CFR1. Software control requires that the

EXT_PWR_DWN pin be forced to a Logic 0 state. In this case,

setting the desired power-down bits (0x00[7:5]) via the serial

input/output port powers down the associated functional block,

whereas clearing the bits restores the function.

Alternatively, all three functions can be simultaneously powered

down via external hardware control through the EXT_PWR_DWN

pin. When this pin is forced to Logic 1, all four circuit blocks are

powered down regardless of the state of the power-down bits;

that is, the independent power-down bits in CFR1 are ignored and

overridden when EXT_PWR_DWN is Logic 1.

The type of power-down activated by asserting the

EXT_PWR_DWN pin depends on the state of CFR1[3]. When

CFR1[3] = 1 (default), assertion of the EXT_PWR_DWN pin

activates full power-down mode. As such, de-asserting the

EXT_PWR_DWN pin necessitates DAC calibration and, if the PLL

is enabled, VCO calibration, as well. Conversely, when CFR1[3]

= 0, assertion of the EXT_PWR_DWN pin activates fast recov-

ery power-down mode. Fast recovery power-down mode main-

tains power to the DAC bias circuitry, the PLL, VCO, and input

clock circuitry. Because the DAC, input clock circuitry and PLL

remain active in fast recovery power-down mode, it is not neces-

sary to perform DAC or VCO calibration after deasserting the

EXT_PWR_DWN pin when CFR1[3] = 0. Although fast recovery

power-down mode offers only incremental power savings compared

to full power-down mode, fast recovery power-down mode allows

the device to awaken from the power-down state very quickly.

Fast recovery power-down is especially beneficial when using the

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