AD9915SLASHPCBZ datasheet(24/51 Pages) AD

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Data Sheet

AD9915

FUNCTIONAL BLOCK DETAIL

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Rev. G | 24 of 51

The primary control for the OSK block is the OSK enable bit

(0x00[8]). When the OSK function is disabled, the OSK input

controls and OSK pin are ignored.

The OSK pin functionality depends on the state of the external OSK

enable bit and the OSK enable bit. When both bits are set to Logic

1 and the OSK pin is Logic 0, the output amplitude is forced to 0;

otherwise, if the OSK pin is Logic 1, the output amplitude is set

by the amplitude scale factor value in one of eight profile registers

depending on the profile pin selection.

Figure 35. OSK Block Diagram

DIGITAL RAMP GENERATOR (DRG)

DRG Overview

To sweep phase, frequency, or amplitude from a defined start point

to a defined endpoint, a completely digital ramp generator is includ-

ed in the AD9915. The DRG makes use of eight control register

bits, three external pins, and five 32-bit registers (see Figure 36).

Figure 36. Digital Ramp Block Diagram

The primary control for the DRG is the digital ramp enable bit

(0x01[19]). When disabled, the other DRG input controls are ignor-

ed and the internal clocks are shut down to conserve power.

The output of the DRG is a 32-bit unsigned data bus that can

be routed to any one of the three DDS signal control parameters,

as controlled by the two digital ramp destination bits in Control

Function Register 2 according to Table 9. The 32-bit output bus is

LSB-aligned with the 32-bit frequency parameter, the 16‑bit phase

parameter, or the 12-bit amplitude parameter, as defined by the

destination bits. When the destination is phase or amplitude, the

unused MSBs are ignored.

Table 9. Digital Ramp Destination

Digital Ramp

Destination Bits

(CFR2[21:20])

DDS Signal Control

Parameter

Allocation of the DDS

Parameter Bits in the

32-bit DRG Output Bus

Frequency

31:0

Phase

15:0

1x1

Amplitude

11:0

1 x means don’t care.

The ramp characteristics of the DRG are fully programmable. This

includes the upper and lower ramp limits, and independent control

of the step size and step rate for both the positive and negative

slope characteristics of the ramp. A detailed block diagram of the

DRG is shown in Figure 37.

The direction of the ramping function is controlled by the DRCTL

pin. The DRG responds differently to the DRCTL pin depending on

the state of the two no-dwell bits (CFR2[18:17]) per Table 10.

The DRG also supports a hold feature controlled via the DRHOLD

pin. When this pin is set to Logic 1, the DRG is stalled at the

last state; otherwise, the DRG operates normally. The DDS signal

control parameters that are not the destination of the DRG are

taken from the active profile.

Table 10. DRCTL Pin Functionality

CFR2[18]

CFR2[17]

Dwell Type

DRCTL Pin Behavior

Hold upper (lower) frequency

limit at end of rising (falling)

ramp

Level sensitive. Logic 0 on the DRCTL pin causes the DRG to initiate a falling ramp,

whereas Logic 1 causes the DRG to initiate a rising ramp.

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