AD9915SLASHPCBZ datasheet(25/51 Pages) AD

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Data Sheet

AD9915

FUNCTIONAL BLOCK DETAIL

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Rev. G | 25 of 51

Table 10. DRCTL Pin Functionality

CFR2[18]

CFR2[17]

Dwell Type

DRCTL Pin Behavior

Return to upper frequency limit

at end of falling ramp

Edge sensitive. A Logic 1 to Logic 0 transition on the DRCTL pin causes the DRG to initiate

a negative slope ramp, which continues uninterrupted (regardless of any further activity on

the DRCTL pin) until the lower limit is reached.

Return to lower frequency limit

at end of rising ramp

Edge sensitive. A Logic 0 to Logic 1 transition on the DRCTL pin causes the DRG to initiate

a positive slope ramp, which continues uninterrupted (regardless of any further activity on

the DRCTL pin) until the upper limit is reached.

Continuous rising and falling

ramp

Edge sensitive. During a positive slope ramp, a Logic 1 to Logic 0 transition on the DRCTL

pin causes the DRG to immediately change the ramp direction to a negative slope using the

negative slope parameters. During a negative slope ramp, a Logic 0 to Logic 1 transition

on the DRCTL pin causes the DRG to immediately change the ramp direction to a positive

slope using the positive slope parameters.

Figure 37. Digital Ramp Generator Detail

DRG Slope Control

The core of the DRG is a 32-bit accumulator clocked by a program-

mable timer. The time base for the timer is the DDS clock, which

operates at 1/16 fSYSCLK. The timer establishes the interval between

successive updates of the accumulator. The positive (+Δt) and

negative (−Δt) slope step intervals are independently programmable

as given by

+Δt= 16PfSYSCLK

−Δt= 16NfSYSCLK

where P and N are the two 16-bit values stored in the 32-bit digital

ramp rate register and control the step interval. N defines the step

interval of the negative slope portion of the ramp. P defines the step

interval of the positive slope portion of the ramp.

The step size of the positive (STEPP) and negative (STEPN) slope

portions of the ramp are 32-bit values programmed into the 32‑bit

rising and falling digital ramp step size registers (0x06 and 0x07).

Program each of the step sizes as an unsigned integer (the hard-

ware automatically interprets STEPN as a negative value). The

relationship between the 32-bit step size values and actual units

of frequency, phase, or amplitude depend on the digital ramp

destination bits. Calculate the actual frequency, phase, or amplitude

step size by substituting STEPN or STEPP for M in the following

equations as required:

FrequencyStep= M232 fSYSCLK

PℎaseStep=πM215(radians)

PℎaseStep=45M213(degrees)

AmplitudeStep= M212 IFS

Note that the frequency units are the same as those that represent

fSYSCLK (MHz, for example). The amplitude units are the same as

those that represent IFS, the full-scale output current of the DAC

(mA, for example).

Although the sweep accumulator has 32 bits of resolution, phase

and amplitude sweeps make use of the 16 LSBs or 12 LSBs of the

sweep accumulator, respectively. Thus, the phase step equations

and the amplitude step equation reflect 16-bit or 12-bit resolution,

accordingly. As such, when programming the associated step size

registers for phase or amplitude sweeps, the user must ensure the

16 MSBs or 20 MSBs, respectively, are programmed with zeros.

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