AD9915SLASHPCBZ datasheet(36/51 Pages) AD

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Data Sheet

AD9915

PARALLEL PROGRAMMING (8-/16-BIT)

analog.com

Rev. G | 36 of 51

The state of the external function pins (F0 to F3) determine the type

of interface used by the AD9915. Pin 28 to Pin 31 are dedicated

function pins. To enable the parallel mode interface set Pin 28 to

Pin 31 to logic low.

Parallel programming consists of eight address lines and either

eight or 16 bidirectional data lines for read/write operations. The

logic state on Pin 22 determines the width of the data bus used.

A logic low on Pin 22 (8-bit mode) sets the data bus width to

eight, and logic high (16-bit mode) sets the data bus width to 16.

In addition, parallel mode has dedicated write/read control inputs. If

16-bit mode is used, the upper byte, Bits[15:8], associates with the

addressed register and the lower byte, Bits[7:0], associates with the

adjacent lower address.

Parallel input/output operation allows write access to each byte of

any register in a single input/output operation. Readback capability

for each register is included to ease designing with the AD9915.

Table 13. Parallel Port Read Timing (See Figure 46)

Parameter

Value

Unit

Test Conditions/Comments

tADV

ns max

Address to data valid time

Table 13. Parallel Port Read Timing (See Figure 46)

Parameter

Value

Unit

Test Conditions/Comments

tAHD

ns min

Address hold time to RD signal inactive

tRDLOV

ns max

RD low to output valid

tRDHOZ

ns max

RD high to data three-state

tRDLOW

ns max

RD signal minimum low time

tRDHIGH

ns max

RD signal minimum high time

Table 14. Parallel Port Write Timing (See Figure 47)

Parameter

Value

Unit

Test Conditions/Comments

tASU

Address setup time to WR signal active

tDSU

3.8

Data setup time to WR signal active

tAHD

Address hold time to WR signal inactive

tDHD

Data hold time to WR signal inactive

tWRLOW

2.1

WR signal minimum low time

tWRHIGH

3.8

WR signal minimum high time

tWR

10.5

Minimum write time

Figure 46. Parallel Port Read Timing Diagram

Figure 47. Parallel Port Write Timing Diagram

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