AD9915SLASHPCBZ datasheet(37/51 Pages) AD

37 / 51 page

Data Sheet

AD9915

MULTIPLE CHIP SYNCHRONIZATION

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Rev. G | 37 of 51

Multichip synchronization applies to an array of AD9915s in which

each device can be programmed independently and then the array

synchronously activated via coincident assertion of the IO_UPDATE

pin. Here, activated means the transfer of the contents of the

AD9915 buffer registers to the active registers (see the General

Serial Input/Output Operation section). Figure 49 shows the general

structure of a typical multichip synchronization system.

To facilitate synchronization, the AD9915 has integrated synchroni-

zation circuitry as shown in Figure 48. The concept of synchroniza-

tion begins with the REFCLK input circuitry, which generates the in-

ternal system clock (SYSCLK) that drives the clock generator block,

as well as the DAC core. Note that a prerequisite for multichip

synchronization is that the signal appearing at the REF_CLK pins of

all devices exhibit time aligned clock edges relative to one another.

The implication being that the system design provides intrinsic

REF_CLK alignment to within one period of SYSCLK. REF_CLK

alignment across devices is necessary to ensure SYSCLK align-

ment across devices.

The SYSCLK signal routes to a clock generator that produces

internal clock signals to accommodate on-chip timing. The clock

generator employs integer dividers, so the internal clock signals

are of lesser frequency than SYSCLK. Thus, the frequency of a

particular internal clock is SYSCLK divided by some integer value,

DIV. Although the internal clocks are synchronous with SYSCLK,

frequency division implies that the rising edge of an internal clock

can relate to the rising edge of any one of DIV SYSCLK edges.

A specific goal of the synchronization system is to make sure the

clock generators in all the AD9915s are in the same state at the

same time. The implication being that the internal clocks across all

AD9915s are edge aligned to the same SYSCLK edge across all

AD9915s (assuming the previously mentioned REFCLK alignment

prerequisite has been met).

In terms of the internal clock signals, the SYNC_CLK signal is of

particular importance, because it provides timing to the DDS core,

the DRG, and the parallel data port. In the case of the SYNC_CLK

signal, DIV = 16, which means the rising edge of the SYNC_CLK

signal can coincide with any one of 16 SYSCLK edges. Thus,

synchronization involves getting the SYNC_CLK signal aligned with

the same SYSCLK edge across multiple AD9915s. The SYNC_CLK

signal is made available at the SYNC_CLK pin, which gives the

user a means to observe and verify synchronization. That is, in

a properly synchronized system, the SYNC_CLK signals of all

devices are edge aligned.

Note that the user can enable or disable the SYNC_CLK pin driver

via CFR2[11] without affecting the state of the internal SYNC_CLK

signal.

In a typical multichip synchronization system, one AD9915 serves

as the synchronization source. In order to function as a synchro-

nization source, the AD9915 includes an integrated sync out gen-

erator block. The sync out generator provides an output signal

(OSYNC) at a frequency of 1/384th of the SYSCLK frequency

with a 67% duty cycle. The OSYNC signal is synchronous with

SYSCLK. Programming CFR2[8] = 1 and CFR2[9] = 1 routes the

OSYNC signal to the SYNC_OUT pin. Note that the OSYNC signal

can be disabled by programming CFR2[8] = 0, which causes the

SYNC_OUT pin to be static Logic 0 (assuming CFR2[9] = 1). It is

not an absolute requirement to use the sync out generator as the

synchronization source, as explained later in this section.

Synchronization involves presetting all the clock generators in all

the AD9915s in a multichip synchronization system to the same

state at the same time. Such is the purpose of the sync in receiver,

which is a CMOS buffer. A clock signal on the SYNC_IN pin routes

to an edge detector that generates ISYNC pulses. Each ISYNC

pulse results from sampling the rising edge of the SYNC_IN signal

with the rising edge of the local SYSCLK. The ISYNC pulses have

a duration of one SYSCLK cycle and a pulse repetition rate equal

to the frequency of the signal at the SYNC_IN pin. Each ISYNC

pulse causes the clock generator to reset its dividers. The reset

state is active for only a single SYSCLK cycle, after which the clock

generator resumes cycling through the state sequence of its divid-

ers at the SYSCLK rate. Thus, the internal clocks are momentarily

set to the reset state coincident with each ISYNC pulse. Assuming

the frequency at the SYNC_IN pin is an integer sub-multiple of

SYSCLK, the resetting of the internal dividers appears transparent

after the initial reset, because the ISYNC pulse occurs at the same

time that the internal dividers naturally assume their reset state.

Under the assumption that the signal appearing at the SYNC_IN

pin of each AD9915 is edge aligned across all AD9915s, then the

internal clocks of all the AD9915s are synchronous to the same

SYSCLK edge across all devices. The adjustable delay feature of

the sync in receiver facilitates correction of small delay errors to

optimize the synchronization system.

Because the edge detector samples the SYNC_IN signal on the

rising edge of SYSCLK, there exists the possibility of the SYNC_IN

signal failing to meet the setup or hold time requirements of the

internal latches in the edge detection circuitry. If this happens, the

ISYNC pulses become unreliable and may cause erratic synchroni-

zation events. To this end, the sync receiver has an adjustable

delay via USR0[2:0] (see Table 15). In the off chance that ISYNC

pulses suffer from setup or hold timing violations leading to erratic

synchronization events, the delay adjustment can be used to move

the edge of the SYNC_IN signal to a stable sampling point.

In a multichip synchronization system, the synchronization source

device and all target devices must be synchronized via the

SYNC_IN pin. In the case of the synchronization source, synchro-

nization is typically accomplished through an external connection

between the SYNC_OUT and SYNC_IN pins. However, this con-

nection is not an absolute requirement, because the synchroniza-

tion signal at the SYNC_IN pin does not need to originate from the

sync out generator. An externally produced SYNC_IN signal can be

used if the following conditions are met:

►

The SYNC_IN signal is traceable to the same source that gener-

ates the signal applied to the REF_CLK inputs.

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