AD9915SLASHPCBZ datasheet(38/51 Pages) AD

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Data Sheet

AD9915

MULTIPLE CHIP SYNCHRONIZATION

analog.com

Rev. G | 38 of 51

►

The frequency of the SYNC_IN signal equals the SYSCLK fre-

quency divided by an integer multiple of 32.

For AD9915s that are synchronization targets, the sync out genera-

tor is superfluous. As such, the option exists for a target device to

have the signal at the SYNC_IN pin loop back to the SYNC_OUT

pin. Loop back of the SYNC_IN signal is in effect when CFR2[9] =

0. SYNC_IN loop back is a useful debug tool for verifying propaga-

tion of the SYNC_IN signal through the sync in receiver.

Figure 48. Synchronization Block Diagram

The typical multichip synchronization system diagram in Figure 49

shows three AD9915s with one operating as the synchronization

source and the others as synchronization targets. The synchroniza-

tion source device, like the target devices, has its SYNC_IN pin

connected to the output of the synchronization distribution and de-

lay equalization block. Taking measures to ensure that the source

and target devices have edge aligned SYNC_IN signals is one of

the fundamental concepts of multichip synchronization.

The synchronization system in Figure 49 relies on the clock distri-

bution and delay equalization block to provide all devices with an

edge aligned REF_CLK signal. Taking measures to ensure that the

source and target devices have edge aligned REF_CLK signals is

another fundamental concept of multichip synchronization.

Synchronization of the AD9915 requires the following conditions:

►

A synchronization signal present at the SYNC_IN pin

►

USR0[6] = 1 (CAL with SYNC)

Within the AD9915, synchronization is handled as part of the DAC

calibration state machine, which executes calibration and synchro-

nization in two sequential segments. The synchronization process

begins by programming CFR4[24] = 1 (DAC CAL enable) followed

by assertion of IO_UPDATE, which initiates the first segment of

the process. Upon completion of the first segment of the process

and given USR0[6] = 1, the state machine waits for the arrival of a

SYNC_IN edge to begin the second segment of the process. The

second segment of the process requires at least 16 cycles of the

SYNC_IN signal to complete the calibration and synchronization

sequence. The absence of a SYNC_IN signal (with USR0[6] =

1) prevents the synchronization process and the DAC calibration

process from completing. See the DAC Calibration Output section

for detail on the time required for the AD9915 to perform DAC

calibration based on the state of USR0[6].

Ambient operating temperature and self heating of the AD9915 are

an important considered in the context of multichip synchronization.

In general, the propagation delay from the SYNC_IN pin to the

clock generator block is fixed for a given operating temperature.

However, large temperature differences between devices or rapid

increases in device temperature at power-up adds to the complexity

of synchronization by virtue of the disparate delays across devices.

Steps must be taken to minimize large temperature gradients or

rapid temperature changes to achieve optimal system performance.

Once a multichip system is synchronized, it is not necessary to con-

tinuously apply a SYNC_IN signal. In fact, the recommendation is to

turn off the source of the SYNC_IN signal after the synchronization

is complete. Turning off the source of the SYNC_IN signal has two

benefits. The first is the elimination of false synchronization events

that might occur from random jitter on the SYNC_IN signal. The

second relates to the DAC calibration circuitry, which continuously

adjusts the timing of the internal clocks to compensate for delay

variation due temperature changes. Interaction between the DAC

calibration circuitry and the synchronization circuitry may result

in random synchronization events when the SYNC_IN signal is

persistent.

Table 15 and Table 16 show the delay time increment associated

with the sync in receiver and the sync out generator, where 0 to 7

equate to the 3-bit value in the associated register.

Table 15. SYNC_IN Delay (USR0[2:0])

Delay Step

Increment, Typ (ns)

0 to 1

0.26

1 to 2

0.15

2 to 3

0.15

3 to 4

0.15

4 to 5

0.15

5 to 6

0.17

6 to 7

0.17

Total delay

1.2

Table 16. SYNC_OUT Delay (USR0[5:3])

Delay Step

Increment, Typ (ns)

0 to 1

0.17

1 to 2

0.3

2 to 3

0.3

3 to 4

0.3

4 to 5

0.3

5 to 6

0.3

6 to 7

0.3

Total delay

1.97

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