AD9915SLASHPCBZ datasheet(26/51 Pages) AD

26 / 51 page

Data Sheet

AD9915

FUNCTIONAL BLOCK DETAIL

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Rev. G | 26 of 51

As described previously, the step interval is controlled by a 16‑bit

programmable timer. There are three events that can cause this

timer to be reloaded prior to the expiration, as follows:

►

A transition of the digital ramp enable bit from cleared to set,

followed by assertion of the IO_UPDATE pin

►

A change of state of the DRCTL pin

►

Anytime the IO_UPDATE pin is asserted while the load LRR at

input/output update bit is set (0x00[15] = 1)

DRG Limit Control

The ramp accumulator is followed by limit control logic that enforces

an upper and lower boundary on the output of the ramp generator.

Under no circumstances does the output of the DRG exceed the

programmed limit values while the DRG is enabled. The limits are

set through the 64-bit digital ramp limit register, comprising a 32-bit

upper limit value and a 32-bit lower limit value. Note that the upper

limit value must be greater than the lower limit value to ensure

normal operation.

For a phase sweep, program the 16 LSBs of the 32-bit upper limit

and lower limit registers with the desired phase value and program

the 16 MSBs of the upper limit and lower limit registers with zeros.

For an amplitude sweep, program the 12 LSBs of the 32-bit upper

limit and lower limit registers with the desired amplitude value and

the 20 MSBs of the upper limit and lower limit registers with zeros.

DRG Accumulator Clear

The ramp accumulator can be cleared (that is, reset to 0) under

program control. When the ramp accumulator is cleared, it forces

the DRG output to the lower limit programmed into the digital ramp

limit register.

With the limit control block embedded in the feedback path of the

accumulator, resetting the accumulator is equivalent to presetting it

to the lower limit value.

Figure 38. Normal Ramp Generation

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