OXCF950 datasheet(44/66 Pages) OXFORD

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OXCF950 rev B DATA SHEET

OXFORD SEMICONDUCTOR, INC.

6.9.3

Automatic In-band Flow Control

When in-band receive flow control is enabled, the UART

will compare the received data with XOFF1 or XOFF2

characters to detect an XOFF condition. When this occurs,

the UART will disable transmission as soon as any current

character transmission is complete. Status bits ISR[4] and

ASR[0] will be set. A level 5 interrupt will occur if enabled

by IER[5]. The UART will then compare all received data

with XON1 or XON2 characters to detect an XON

condition. When this occurs, the UART will re-enable

transmission and status bits ISR[4] and ASR[0] will be

cleared.

Any valid XON/XOFF characters will not be written into the

RHR. An exception to this rule occurs if special character

detection is enabled and an XOFF2 character is received

that is a valid XOFF. In this instance, the character will be

written into the RHR.

The received status (i.e. parity and framing) of XON/XOFF

characters does not have to be valid for these characters to

be accepted as valid matches.

When the 'XON Any' flag (MCR[5]) is set, any received

character is accepted as a valid XON condition and the

transmitter will be re-enabled. The received data will be

transferred to the RHR.

When in-band transmit flow control is enabled, the RFL will

be sampled whenever the transmitter is idle (briefly,

between characters, or when the THR is empty) and an

XON/XOFF character may be inserted into the data stream

if needed. Initially, remote transmissions are enabled and

hence ASR[1] is clear. If ASR[1] is clear and the RFL has

passed the upper trigger level (i.e. is above the trigger

level), XOFF will be sent and ASR[1] will be set. If ASR[1]

is set and the RFL falls below the lower trigger level, XON

will be sent and ASR[1] will be cleared.

If transmit flow control is disabled after an XOFF has been

sent, an XON will be sent automatically.

6.9.4

Automatic Out-of-band Flow Control

Automatic RTS/CTS flow control is selected by different

means, depending on whether the UART is in Enhanced or

non-Enhanced mode. When in non-Enhanced mode,

MCR[5] enables both RTS and CTS flow control. When in

Enhanced mode, EFR[6] enables automatic RTS flow

control and EFR[7] enables automatic CTS flow control.

This allows software compatibility with both 16C650 and

16C750 drivers.

When automatic CTS flow control is enabled and the CTS#

input becomes active, the UART will disable transmission

as soon as any current character transmission is complete.

Transmission is resumed whenever the CTS# input

becomes inactive.

When automatic RTS flow control is enabled, the RTS# pin

will be forced inactive when the RFL reaches the upper

trigger level and will return to active when the RFL falls

below the lower trigger level. The automatic RTS# flow

control is ANDed with MCR[1] and hence is only

operational when MCR[1]=1. This allows the software

driver to override the automatic flow control and disable the

remote transmitter regardless by setting MCR[1]=0 at any

time.

Automatic DTR/DSR flow control behaves in the same

manner as RTS/CTS flow control but is enabled by

ACR[3:2], regardless of whether or not the UART is in

Enhanced mode.

6.10 Baud Rate Generation

6.10.1 General Operation

The UART contains a programmable baud rate generator

that is capable of taking any clock input from DC to 60MHz

and dividing it by any 16-bit divisor number from 1 to 65535

written into the DLM (MSB) and DLL (LSB) registers. In

addition to this, a clock prescaler register is provided which

can further divide the clock by values in the range 1.0 to

31.875 in steps of 0.125. Also, a further feature is the

Times Clock Register ‘TCR’ which allows the sampling

clock to be set to any value between 4 and 16.

These clock options allow for highly flexible baud rate

generation capabilities from almost any input clock

frequency (up to 60MHz). The actual transmitter and

receiver baud rate is calculated as follows:

prescaler

Divisor

InputClock

BaudRate

Where:

= Sample clock values defined in TCR[3:0]

Divisor = DLL + ( 256 x DLM )

Prescaler = 1 when MCR[7] = ‘0’ else:

= M + ( N / 8 ) where:

= CPR[7:3] (Integer part – 1 to 31)

= CPR[2:0] (Fractional part – 0.000 to 0.875 )

See next section for a discussion of the clock prescaler and

times clock register.

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