OXCF950 datasheet(16/66 Pages) OXFORD

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OXCF950 rev B DATA SHEET

OXFORD SEMICONDUCTOR, INC.

Each of the local configuration registers are explained in the following sections. The offsets assume normal or local bus mode,

and these are the offsets that should be used when accessing the registers via the EEPROM.

EEPROM Status and Control register ‘ESC’(Offset 0x08)

This register defines the control on the serial EEPROM. The individual bits are described in Table 7.

Read/Write

Bits

Description

EEPROM

PCMCIA

Reset

7:6

Reserved

000

EEPROM Overrun.

Set when an invalid EEPROM image causes the end of the EEPROM to be

read before the end of the programming sequence. In this state the

OXCF950 is set as though no EEPROM is attached.

This feature is new to OXCF950 rev B

EEPROM Data In.

For reads from the EEPROM this input bit is the output-data (DO) of the

external EEPROM connected to EE_DI pin

EEPROM Data Out.

For writes to the EEPROM, this output bit feeds the input-data of the

external EEPROM (DI). This bit is output on the devices EE_DO and

clocked into the EEPROM by EE_CK

R/W

EEPROM Clock.

For reads or writes to the external EEPROM toggle this bit to generate an

EEPROM clock (EE_CK pin)

R/W

EEPROM Chip Select.

When ‘1’ the EEPROM chip select pin EE_CS is activated (high). When ‘0’

EE_CS is de-activated (low)

R/W

EEPROM Valid

A ‘1’ indicates that a valid EEPROM program header is present

Table 7: EEPROM Status and Control Register

Multi-Purpose I/O Configuration register ‘MIC’ (Offset 0x09)

This register configures the operation for the multi-purpose I/O pins ‘MIO[1:0]’ as follows

Read/Write

Bits

Description

EEPROM

PCMCIA

Reset

7:4

Reserved

0000

3:2

MIO1 Configuration register

00 -> MIO1 is a non-inverting input pin

01 -> MIO1 is an inverting input pin

10 -> MIO1 is an output pin driving ‘0’

11 -> MIO1 is an output pin driving ‘1’

R/W

1:0

MIO0 Configuration register

00 -> MIO0 is a non-inverting input pin

01 -> MIO0 is an inverting input pin

10 -> MIO0 is an output pin driving ‘0’

11 -> MIO0 is an output pin driving ‘1’

R/W

Table 8: Multi Purpose I/O Configuration Register

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