OXCF950 datasheet(18/66 Pages) OXFORD

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DS-0027 Feb 06

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OXCF950 rev B DATA SHEET

OXFORD SEMICONDUCTOR, INC.

Interrupt Status and Control register ‘ISR’ (Offset 0x0C)

This register controls the assertion of interrupts from the User I/O pins (MIO[1:0]) as well as returning the internal status of the

interrupt sources.

Read/Write

Bits

Description

EEPROM

PCMCIA

Reset

7:5

Reserved

000

UART Interrupt status

This bit reflects the state of the internal UART interrupt

MIO[1] interrupt mask

When set to ‘1’ allows pin MIO[1] to assert an interrupt on the devices

IREQ# pin. The state of the MIO[1] signal that causes an interrupt is

dependent upon the polarity set by the register fields MIC[3:2].

R/W

MIO[0] interrupt mask

When set to ‘1’ allows pin MIO[0] to assert an interrupt on the devices

IREQ# pin. The state of the MIO[0] signal that causes an interrupt is

dependent upon the polarity set by the register fields MIC[1:0].

R/W

MIO1 Internal state

This bit reflects the state of the internal MIO[1]. The internal MIO[1] signal

reflects the non-inverted or inverted state of MIO[1] pin

MIO0 Internal state

This bit reflects the state of the internal MIO[0]. The internal MIO[0] signal

reflects the non-inverted or inverted state of MIO[0] pin

Table 11: Interrupt Status Register

Soft UART/Local Bus reset register ‘SRT’ (Offset 0x0D)

This register controls the soft reset passed to the UART and local bus reset. These reset lines are in addition to the soft reset

that may be produced by the host (bit[7] of the COR register in attribute memory space). Note that the local bus reset is used in

Local Bus mode only and not in Normal mode. Note these bits are not self-clearing.

Read/Write

Bits

Description

EEPROM

PCMCIA

Reset

7:2

Reserved

000000

Active high soft reset for UART

R/W

Active high soft reset for Local Bus

R/W

Table 12: Soft UART / Local Bus Reset (LB reset used in Local Bus Mode only)

Generic Mode Control register ‘GMC’ (Offset 0x0E)

This register provides EEPROM control for the pin-selectable Generic mode. When set, only the bottom 3 address bits are

decoded for UART access, and paging is required to switch to configuration registers. It is up to the user to ensure the CIS tuples

also request only an 8 bit address range if this is programmed via the EEPROM (i.e. CIS entries will be needed as well).

Read/Write

Bits

Description

EEPROM

PCMCIA

Reset

Generic Mode Address Decode

Enables Generic Mode decoding when ‘1’. This should only be set in

Normal mode (MODE = ‘0’)

This feature is new to OXCF950 rev B

Table 13: Generic Mode Control

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