OXCF950 datasheet(37/66 Pages) OXFORD

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DS-0027 Feb 06

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OXCF950 rev B DATA SHEET

OXFORD SEMICONDUCTOR, INC.

In all cases, a receiver data interrupt will be generated (if

enabled) if the Receiver FIFO Level (‘RFL’) reaches the

upper trigger level L2.

950 Mode:

When 950 trigger levels are enabled (ACR[5]=1), more

flexible trigger levels can be set by writing to the TTL, RTL,

FCL and FCH (see section 6.11) hence ignoring FCR[7:6].

6.5

Line Control & Status

6.5.1

False Start Bit Detection

On the falling edge of a start bit, the receiver will wait for

1/2 bit and re-synchronise the receiver’s sampling clock

onto the centre of the start bit. The start bit is valid if the

SIN line is still low at this mid-bit sample and the receiver

will proceed to read in a data character. Verifying the start

bit prevents the receiver from assembling a false data

character due to a low going noise spike on the SIN input.

Once the first stop bit has been sampled, the received data

is transferred to the RHR and the receiver will then wait for

a low transition on SIN signifying the next start bit.

The receiver will continue receiving data even if the RHR is

full or the receiver has been disabled (see section 6.11.3)

in order to maintain framing synchronisation. The only

difference is that the received data does not get transferred

to the RHR.

6.5.2

Line Control Register ‘LCR’

The LCR specifies the data format that is common to both

transmitter and receiver. Writing 0xBF to LCR enables

access to the EFR, XON1, XOFF1, XON2 and XOFF2,

DLL and DLM registers. This value (0xBF) corresponds to

an unused data format. Writing the value 0xBF to LCR will

set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the

data format of the transmitter and receiver data is not

affected. Write the desired LCR value to exit from this

selection.

LCR[1:0]: Data length

LCR[1:0] Determines the data length of serial characters.

Note however, that these values are ignored in 9-bit data

framing mode, i.e. when NMR[0] is set.

LCR[1:0]

Data length

5 bits

6 bits

7 bits

8 bits

Table 31: LCR Data Length Configuration

LCR[2]: Number of stop bits

LCR[2] defines the number of stop bits per serial character.

LCR[2]

Data length

No. stop

bits

5,6,7,8

1.5

6,7,8

Table 32: LCR Stop Bit Number Configuration

LCR[5:3]: Parity type

The selected parity type will be generated during

transmission and checked by the receiver, which may

produce a parity error as a result. In 9-bit mode parity is

disabled and LCR[5:3] is ignored.

LCR[5:3]

Parity type

xx0

No parity bit

001

Odd parity bit

011

Even parity bit

101

Parity bit forced to 1

111

Parity bit forced to 0

Table 33: LCR Parity Configuration

LCR[6]: Transmission break

logic 0

⇒ Break transmission disabled.

logic 1

⇒ Forces the transmitter data output SOUT low

to alert the communication terminal, or send

zeros in IrDA mode.

It is the responsibility of the software driver to ensure that

the break duration is longer than the character period for it

to be recognised remotely as a break rather than data.

LCR[7]: Divisor latch enable

logic 0

⇒ Access to DLL and DLM registers disabled.

logic 1

⇒ Access to DLL and DLM registers enabled.

6.5.3

Line Status Register ‘LSR’

This register provides the status of data transfer to CPU.

LSR[0]: RHR data available

logic 0

⇒ RHR is empty: no data available

logic 1

⇒ RHR is not empty: data is available to be read.

LSR[1]: RHR overrun error

logic 0

⇒ No overrun error.

logic 1

⇒ Data was received when the RHR was full. An

overrun error has occurred. The error is

flagged when the data would normally have

been transferred to the RHR.

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