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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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OXCF950 датащи(PDF) 32 Page - Oxford Semiconductor |
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OXCF950 датащи(HTML) 32 Page - Oxford Semiconductor |
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32 / 66 page  DS-0027 Feb 06 External—Free Release Page 32 of 66 OXCF950 rev B DATA SHEET OXFORD SEMICONDUCTOR, INC. 6.2 Register Description Tables The three address lines select the various registers in the UART. Since there are more than 8 registers, selection of the registers is also dependent on the state of the Line Control Register ‘LCR’ and Additional Control Register ‘ACR’: 1. LCR[7]=1 enables the divider latch registers DLL and DLM. 2. LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection. 3. ACR[7]=1 enables access to the 950 specific registers. 4. ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 34. Register Name Address R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 THR 1 000 W Data to be transmitted RHR 1 000 R Data received IER 1,2 650/950 Mode CTS interrupt mask RTS interrupt mask Special Char. Detect 550/750 Mode 001 R/W Unused Alternate sleep mode Sleep mode Modem interrupt mask Rx Stat interrupt mask THRE interrupt mask RxRDY interrupt mask FCR 3 650 mode RHR Trigger Level THR Trigger Level 750 mode RHR Trigger Level FIFO Size Unused 950 mode 010 W Unused DMA Mode / Tx Trigger Enable Flush THR Flush RHR Enable FIFO ISR 3 010 R FIFOs enabled Interrupt priority (Enhanced mode) Interrupt priority (All modes) Interrupt pending LCR 4 011 R/W Divisor latch access Tx break Force parity Odd / even parity Parity enable Number of stop bits Data length MCR 3,4 550/750 Mode Unused CTS & RTS Flow Control 650/950 Mode 100 R/W Baud prescale IrDA mode XON-Any Internal Loop Back Enable OUT2 (Int En) OUT1 RTS DTR LSR 3,5 Normal Data Error Tx Empty THR Empty Rx Break Framing Error Parity Error Overrun Error RxRDY 9-bit data mode 101 R 9th Rx data bit MSR 3 110 R DCD RI DSR CTS Delta DCD Trailing RI edge Delta DSR Delta CTS SPR 3 Normal Temporary data storage register and Indexed control register offset value bits 9-bit data mode 111 R/W Unused 9th Tx data bit Additional Standard Registers – These registers require divisor latch access bit (LCR[7]) to be set to 1. DLL 000 R/W Divisor latch bits [7:0] (Least significant byte) DLM 001 R/W Divisor latch bits [15:8] (Most significant byte) Table 24: Standard 550 Compatible Registers |
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