OXCF950 datasheet(31/66 Pages) OXFORD

31 / 66 page

DS-0027 Feb 06

External—Free Release

Page 31 of 66

OXCF950 rev B DATA SHEET

OXFORD SEMICONDUCTOR, INC.

enabled using the Additional Control Register ‘ACR’ (see

section 6.11.3). In addition to larger FIFOs and higher baud

rates, the enhancements of the 950 over the 16C654 are:

•

Selectable arbitrary trigger levels for the receiver and

transmitter FIFO interrupts

•

Improved automatic flow control using selectable

arbitrary thresholds

•

DSR#/DTR# automatic flow control

•

Transmitter and receiver can be optionally disabled

•

Software reset of device

•

Readable FIFO fill levels

•

Optional generation of an RS-485 buffer enable signal

•

Four-byte device identification (0x16C95008)

•

Readable status for automatic in-band and out-of-

band flow control

•

External 1x clock modes (see section 6.10.4)

•

Flexible “M N/8” clock prescaler (see section 6.10.2)

•

Programmable sample clock to allow data rates up to

15 Mbps (see section 6.10.3)

•

9-bit data mode

The 950 trigger levels are enabled when ACR[5] is set (bits

4 to 7 of FCR are ignored). Then arbitrary trigger levels can

be defined in RTL, TTL, FCL and FCH registers (see

section 6.11). The Additional Status Register (‘ASR’) offers

flow control status for the local and remote transmitters.

FIFO levels are readable using RFL and TFL registers.

The UART has a flexible prescaler capable of dividing the

system clock by any value between 1 and 31.875 in steps

of 0.125. It divides the system clock by an arbitrary value in

“M N/8” format, where M and N are 5 and 3-bit binary

numbers programmed in CPR[7:3] and CPR[2:0]

respectively. This arrangement offers a great deal of

flexibility when choosing an input clock frequency to

synthesize arbitrary baud rates. The default division value

is 4 to provide backward compatibility with 16C650

devices.

The user may apply an external 1x (or Nx) clock for the

transmitter and receiver to the RI# and DSR# pin

respectively. The transmitter clock may be asserted on the

DTR# pin. The external clock options are selected through

the CKS register (offset 0x02 of ICR).

It is also possible to define the over-sampling rate used by

the transmitter and receiver clocks. The 16C450/16C550

and compatible devices employ 16 times over-sampling,

i.e. There are 16 clock cycles per bit. However, the 950 can

employ any over-sampling rate from 4 to 16 by

programming the TCR register. This allows the data rates

to be increased to 460.8 Kbps using a 1.8432MHz clock, or

15 Mbps using a 60 MHz clock. The default value after a

reset for this register is 0x00, which corresponds to a 16

cycle sampling clock. Writing 0x01, 0x02 or 0x03 will also

result in a 16 cycle sampling clock. To program the value to

any value from 4 to 15 it is necessary to write this value

into TCR i.e. to set the device to a 13 cycle sampling clock

it would be necessary to write 0x0D to TCR. For further

information see sections 6.10.3.

The 950 also offers 9-bit data frames for multi-drop

industrial applications.

OXCF950 датащи(PDF) 31 Page - Oxford Semiconductor

OXCF950 датащи(HTML) 31 Page - Oxford Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

датащи скачать

ссылки URL