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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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OXCF950 датащи(PDF) 34 Page - Oxford Semiconductor |
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OXCF950 датащи(HTML) 34 Page - Oxford Semiconductor |
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34 / 66 page  DS-0027 Feb 06 External—Free Release Page 34 of 66 OXCF950 rev B DATA SHEET OXFORD SEMICONDUCTOR, INC. Register Name SPR Offset 10 R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indexed Control Register Set ACR 0x00 R/W Addit- ional Status Enable ICR Read Enable 950 Trigger Level Enable DTR definition and control Auto DSR Flow Control Enable Tx Disable Rx Disable CPR 0x01 R/W 5 Bit “integer” part of clock prescaler 3 Bit “fractional” part of clock prescaler TCR 0x02 R/W Unused 4 Bit N-times clock selection bits [3:0] CKS 0x03 R/W Tx 1x Mode Tx CLK Select BDOUT on DTR DTR 1x Tx CLK Rx 1x Mode Disable BDOUT Receiver Clock Sel[1:0] TTL 0x04 R/W Unused Transmitter Interrupt Trigger Level (0-127) RTL 0x05 R/W Unused Receiver Interrupt Trigger Level (1-127) FCL 0x06 R/W Unused Automatic Flow Control Lower Trigger Level (0-127) FCH 0x07 R/W Unused Automatic Flow Control Higher Trigger level (1-127) ID1 0x08 R Hardwired ID byte 1 (0x16) ID2 0x09 R Hardwired ID byte 1 (0xC9) ID3 0x0A R Hardwired ID byte 1 (0x50) REV 0x0B R Hardwired revision byte (0x08) CSR 0x0C W Writing 0x00 to this register will reset the UART (Except the CKS and CKA registers) NMR 0x0D R/W Unused 9th Bit SChar 4 9th Bit Schar 3 9th Bit SChar 2 9th Bit SChar 1 9th-bit Int. En. 9 Bit Enable MDM 0x0E R/W Unused Δ DCD Wakeup disable Trailing RI edge disable Δ DSR Wakeup disable Δ CTS Wakeup disable RFC 0X0F R FCR[7] FCR[6] FCR[5] FCR[4] FCR[3] FCR[2] FCR[1] FCR[0] GDS 0X10 R Unused Good Data Status DMS 0x11 R/W Force internal TxRdy inactive Force internal RxRdy inactive Unused Internal TxRdy status ( R ) Internal RxRdy status ( R ) PIDX 0x12 R Hardwired Port Index ( 0x00 ) CKA 0x13 R/W Unused Res. Write ‘0’ Res. Write ‘0’ Invert DTR signal Invert internal tx clock Invert internal rx clock MDR 0xFE R/W Unused Cfg Paging control Table 27: Indexed Control Register Set |
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