AT83SND2CMP3 datasheet(30/97 Pages) ATMEL

30 / 97 page

AT83SND2CMP3

7524B–MP3–05/06

Note:

Refer to DAC_MC register Table 38. for signal description

Master Clock and Sampling

Frequency Selection

The following table describes the different modes available for master clock and sam-

pling frequency selection by setting OVRSEL bit in DAC_CSFC register (refer to Table

39.).

Table 25.

Master Clock selection

The selection of input sample size is done using the NBITS 1:0 in DAC_MISC register

(refer to Table 40.) according to Table 26.

Table 26.

Input Sample Size Selection

The selection between modes is done using DINTSEL 1:0 in DAC_MISC register (refer

to Table 40.) according to Table 27.

Table 27.

Format Selection

De-emphasis and dither

enable

The circuit features a de-emphasis filter for the playback channel. To enable the de-

emphasis filtering, DEEMPEN must be set to high.

Likewise, the dither option (added in the playback channel) is enabled by setting the

DITHEN signal to High.

Signal

Description

LMSMIN1

Left Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to disable

LMSMIN2

Left Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to

disable

RMSMIN1

Right Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to

disable

RMSMIN2

Right Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to

disable

OVRSEL

Master Clock

0256 x FS

1384 x FS

NBITS 1:0

Format

16 bits

18 bits

20 bits

DINTSEL 1:0

Format

I2S Justified

MSB Justified

LSB Justified

AT83SND2CMP3 датащи(PDF) 30 Page - ATMEL Corporation

AT83SND2CMP3 датащи(HTML) 30 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

датащи скачать

ссылки URL