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AT83SND2CMP3 датащи(PDF) 91 Page - ATMEL Corporation |
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AT83SND2CMP3 датащи(HTML) 91 Page - ATMEL Corporation |
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91 / 97 page ![]() 91 AT83SND2CMP3 7524B–MP3–05/06 External Clock Drive and Logic Level References Definition of symbols Table 67. External Clock Timing Symbol Definitions Timings Table 68. External Clock AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85°C Waveforms Figure 91. External Clock Waveform Figure 92. AC Testing Input/Output Waveforms Note: 1. During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a logic 0. 2. Timing measurements are made on all outputs at V IH min for a logic 1 and VIL max for a logic 0. Figure 93. Float Waveforms Signals Conditions CClock H High LLow X No Longer Valid Symbol Parameter Min Max Unit T CLCL Clock Period 50 ns T CHCX High Time 10 ns T CLCX Low Time 10 ns T CLCH Rise Time 3 ns T CHCL Fall Time 3 ns T CR Cyclic Ratio in X2 mode 40 60 % 0.45 V T CLCL V DD - 0.5 V IH1 V IL T CHCX T CLCH T CHCL T CLCX 0.45 V V DD - 0.5 0.7 V DD 0.3 V DD V IH min V IL max INPUTS OUTPUTS V LOAD V OH - 0.1 V V OL + 0.1 V V LOAD + 0.1 V V LOAD - 0.1 V Timing Reference Points |
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