AT83SND2CMP3 datasheet(68/97 Pages) ATMEL

68 / 97 page

AT83SND2CMP3

7524B–MP3–05/06

Internal Baud Rate Generator

When using the Internal Baud Rate Generator, the Baud Rate is derived from the over-

flow of the timer. As shown in Figure 58 the Internal Baud Rate Generator is an 8-bit

auto-reload timer fed by the peripheral clock or by the peripheral clock divided by 6

depending on the SPD bit in BDRCON register. The Internal Baud Rate Generator is

enabled by setting BBR bit in BDRCON register. SMOD1 bit in PCON register allows

doubling of the generated baud rate.

Figure 58.

Internal Baud Rate Generator Block Diagram

Synchronous Mode

(Mode 0)

Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0

capabilities of a device with shift registers. The transmit data (TXD) pin outputs a set of

eight clock pulses while the receive data (RXD) pin transmits or receives a Byte of data.

The 8-bit data are transmitted and received least-significant bit (LSB) first. Shifts occur

at a fixed Baud Rate (see Section "Baud Rate Selection (Mode 0)", page 69). Figure 59

shows the serial port block diagram in Mode 0.

Figure 59.

Serial I/O Port Block Diagram (Mode 0)

Transmission (Mode 0)

To start a transmission mode 0, write to SCON register clearing bits SM0, SM1.

As shown in Figure 60, writing the Byte to transmit to SBUF register starts the transmis-

sion. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle

composed of a high level then low level signal on TXD. During the eighth clock cycle the

MSB (D7) is on the RXD pin. Then, hardware drives the RXD pin high and asserts TI to

indicate the end of the transmission.

Overflow

SPD

BDRCON.1

BRG

(8 bits)

BRL

(8 bits)

PER

CLOCK

÷ 6

IBRG

CLOCK

BRR

BDRCON.4

SMOD1

PCON.7

÷ 2

To serial

Port

BRG

CLOCK

TXD

RXD

SBUF Tx SR

SBUF Rx SR

SM1

SCON.6

SM0

SCON.7

Mode Decoder

M3 M2 M1 M0

Mode

Controller

SCON.0

SCON.1

PER

CLOCK

Baud Rate

Controller

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