| поискавой системы для электроныых деталей |
|
56F803 датащи(PDF) 17 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
56F803 датащи(HTML) 17 Page - Freescale Semiconductor, Inc |
|
17 / 57 page ![]() 56F803 Technical Data, Rev. 16 12 Freescale Semiconductor 2.5 Interrupt and Program Control Signals Table 2-7 Data Bus Signals No. of Pins Signal Name Signal Type State During Reset Signal Description 16 D0–D15 Input/O utput Tri-stated Data Bus— D0–D15 specify the data for external Program or Data memory accesses. D0–D15 are tri-stated when the external bus is inactive. Internal pull-ups may be active. Table 2-8 Bus Control Signals No. of Pins Signal Name Signal Type State During Reset Signal Description 1 PS Output Tri-stated Program Memory Select—PS is asserted low for external Program memory access. 1 DS Output Tri-stated Data Memory Select—DS is asserted low for external Data memory access. 1 WR Output Tri-stated Write Enable—WR is asserted during external memory write cycles. When WR is asserted low, pins D0–D15 become outputs and the device puts data on the bus. When WR is deasserted high, the external data is latched inside the external device. When WR is asserted, it qualifies the A0–A15, PS, and DS pins. WR can be connected directly to the WE pin of a Static RAM. 1 RD Output Tri-stated Read Enable—RD is asserted during external memory read cycles. When RD is asserted low, pins D0–D15 become inputs and an external device is enabled onto the device data bus. When RD is deasserted high, the external data is latched inside the controller. When RD is asserted, it qualifies the A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a Static RAM or ROM. Table 2-9 Interrupt and Program Control Signals No. of Pins Signal Name Signal Type State During Reset Signal Description 1 IRQA Input (Schmitt) Input External Interrupt Request A—The IRQA input is a synchronized external interrupt request indicating an external device is requesting service. It can be programmed to be level-sensitive or negative-edge- triggered. 1 IRQB Input (Schmitt) Input External Interrupt Request B—The IRQB input is an external interrupt request indicating an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |