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56F803 датащи(PDF) 30 Page - Freescale Semiconductor, Inc |
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56F803 датащи(HTML) 30 Page - Freescale Semiconductor, Inc |
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30 / 57 page ![]() Flash Memory Characteristics 56F803 Technical Data, Rev. 16 Freescale Semiconductor 25 Figure 3-4 Flash Program Cycle Cumulative program HV period2 Thv –3 – ms Figure 3-4 Program hold time3 Tpgh –– – Figure 3-4 Address/data set up time3 Tads –– – Figure 3-4 Address/data hold time3 Tadh –– – Figure 3-4 1. One cycle is equal to an erase program and read. 2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be programmed twice before next erase. 3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater. *The Flash interface unit provides registers for the control of these parameters. Table 3-7 Flash Timing Parameters (Continued) Operating Conditions: V SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Typ Max Unit Figure XADR YADR YE DIN PROG NVSTR Tnvs Tpgs Tadh Tprog Tads Tpgh Tnvh Trcv Thv IFREN XE |
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