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56F803 датащи(PDF) 41 Page - Freescale Semiconductor, Inc

номер детали 56F803
подробное описание детали  16-bit Digital Signal Controllers
PDF  57 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

56F803 датащи(HTML) 41 Page - Freescale Semiconductor, Inc

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56F803 Technical Data, Rev. 16
36
Freescale Semiconductor
Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service
3.8 Serial Peripheral Interface (SPI) Timing
Table 3-12 SPI Timing1
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
tC
50
25
—
—
ns
ns
Figures 3-18, ,
3-20, 3-21
Enable lead time
Master
Slave
tELD
—
25
—
—
ns
ns
Figure 3-21
Enable lag time
Master
Slave
tELG
—
100
—
—
ns
ns
Figure 3-21
Clock (SCLK) high time
Master
Slave
tCH
17.6
12.5
—
—
ns
ns
Figures 3-18, ,
3-20, 3-21
Clock (SCLK) low time
Master
Slave
tCL
24.1
25
—
—
ns
ns
Figures 3-18, ,
3-20, 3-21
Data set-up time required for inputs
Master
Slave
tDS
20
0
—
—
ns
ns
Figures 3-18, ,
3-20, 3-21
Data hold time required for inputs
Master
Slave
tDH
0
2
—
—
ns
ns
Figures 3-18, ,
3-20, 3-21
Access time (time to data active from high-impedance
state)
Slave
tA
4.8
15
ns
Figure 3-21
Disable time (hold time to high-impedance state)
Slave
tD
3.7
15.2
ns
Figure 3-21
Instruction Fetch
IRQA
A0–A15
PS, DS,
RD, WR
First IRQA Interrupt
tIRQ
tII



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