поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

56F803 датащи(PDF) 37 Page - Freescale Semiconductor, Inc

номер детали 56F803
подробное описание детали  16-bit Digital Signal Controllers
PDF  57 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

56F803 датащи(HTML) 37 Page - Freescale Semiconductor, Inc

Back Button 56F803 Datasheet HTML 33Page - Freescale Semiconductor, Inc 56F803 Datasheet HTML 34Page - Freescale Semiconductor, Inc 56F803 Datasheet HTML 35Page - Freescale Semiconductor, Inc 56F803 Datasheet HTML 36Page - Freescale Semiconductor, Inc 56F803 Datasheet HTML 37Page - Freescale Semiconductor, Inc 56F803 Datasheet HTML 38Page - Freescale Semiconductor, Inc 56F803 Datasheet HTML 39Page - Freescale Semiconductor, Inc 56F803 Datasheet HTML 40Page - Freescale Semiconductor, Inc 56F803 Datasheet HTML 41Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 37 / 57 page
background image
56F803 Technical Data, Rev. 16
32
Freescale Semiconductor
Figure 3-11 External Bus Asynchronous Timing
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1.
Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2.
Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing 1, 5
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Max
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—21
ns
Figure 3-12
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
tRA
275,000T
128T
—
—
ns
ns
Figure 3-12
RESET De-assertion to First External Address Output
tRDA
33T
34T
ns
Figure 3-12
A0–A15,
PS, DS
(See Note)
WR
D0–D15
RD
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Data In
Data Out
tAWR
tARDA
tARDD
tRDA
tRD
tRDRD
tRDWR
tWRWR
tWR
tDOS
tWRD
tWRRD
tAD
tDOH
tDRD
tRDD



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com