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56F803 датащи(PDF) 46 Page - Freescale Semiconductor, Inc |
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56F803 датащи(HTML) 46 Page - Freescale Semiconductor, Inc |
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46 / 57 page ![]() Quadrature Decoder Timing 56F803 Technical Data, Rev. 16 Freescale Semiconductor 41 Figure 3-22 Timer Timing 3.10 Quadrature Decoder Timing Timer output high/low period POUTHL 1T — ns 1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design. Table 3-14 Quadrature Decoder Timing1,2 Operating Conditions: V SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz 1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12. ns. VSS = 0 V, VDD = 3.0 – 3.6V, TA = –40° to +85°C, CL ≤ 50pF. 2. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit Quadrature input period PIN 8T+12 — ns Quadrature input high/low period PHL 4T+6 — ns Quadrature phase period PPH 2T+3 — ns Table 3-13 Timer Timing1, 2 Operating Conditions: V SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz Timer Inputs Timer Outputs PIN PINHL PINHL POUT POUTHL POUTHL |
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