AT83SND2CMP3B datasheet(61/241 Pages) ATMEL

61 / 241 page

4341F–MP3–03/06

AT8xC51SND2C/MP3B

12.3

Watchdog Operation

After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and E1h into

the WDTRST register. As soon as it is enabled, there is no way except the chip reset to disable

it. If it is not cleared using the previous sequence, the WDT overflows and forces a chip reset.

This overflow generates a high level 96 oscillator periods pulse on the RST pin to globally reset

the application (refer to Section “Power Management”, page 47).

The WDT time-out period can be adjusted using WTO2:0 bits located in the WDTPRG register

accordingly to the formula shown in Figure 12-3. In this formula, WTOval represents the decimal

value of WTO2:0 bits. Table 12-1 reports the time-out period depending on the WDT frequency.

Figure 12-3. WDT Time-Out Formula

Notes:

1. These frequencies are achieved in X1 mode or in X2 mode when WTX2 = 1:

WDT = FOSC ÷ 2.

2. These frequencies are achieved in X2 mode when WTX2 = 0: F

WDT = FOSC.

12.3.1

WDT Behavior during Idle and Power-down Modes

Operation of the WDT during power reduction modes deserves special attention.

The WDT continues to count while the AT8xC51SND2C is in Idle mode. This means that you

must dedicate some internal or external hardware to service the WDT during Idle mode. One

approach is to use a peripheral Timer to generate an interrupt request when the Timer over-

flows. The interrupt service routine then clears the WDT, reloads the peripheral Timer for the

next service period and puts the AT8xC51SND2C back into Idle mode.

The Power-down mode stops all phase clocks. This causes the WDT to stop counting and to

hold its count. The WDT resumes counting from where it left off if the Power-down mode is ter-

minated by INT0, INT1 or keyboard interrupt. To ensure that the WDT does not overflow shortly

after exiting the Power-down mode, it is recommended to clear the WDT just before entering

Power-down mode.

The WDT is cleared and disabled if the Power-down mode is terminated by a reset.

Table 12-1.

WDT Time-Out Computation

WTO2

WTO1

WTO0

WDT (ms)

6 MHz(1)

8 MHz(1)

10 MHz(1)

12 MHz(2)

16 MHz(2)

20 MHz(2)

16.38

12.28

9.83

8.19

6.14

4.92

32.77

24.57

19.66

16.38

12.28

9.83

65.54

49.14

39.32

32.77

24.57

19.66

011131.07

98.28

78.64

65.54

49.14

39.32

100262.14

196.56

157.29

131.07

98.28

78.64

101524.29

393.1

314.57

262.14196.56

157.29

1049

786.24

629.15

524.29

393.12

314.57

2097

1572

1258

1049

786.24

629.15

WDTTO

FWDT

⋅ ((214 ⋅ 2WTOval) – 1)

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