AT83SND2CMP3B datasheet(49/241 Pages) ATMEL

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4341F–MP3–03/06

AT8xC51SND2C/MP3B

10.3

Idle Mode

Idle mode is a power reduction mode that reduces the power consumption. In this mode, pro-

gram execution halts. Idle mode freezes the clock to the CPU at known states while the

peripherals continue to be clocked (refer to section “Oscillator”, page 13). The CPU status

before entering Idle mode is preserved, i.e., the program counter and program status word reg-

ister retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also

retained. The status of the Port pins during Idle mode is detailed in Table 10-1.

10.3.1

Entering Idle Mode

To enter Idle mode, the user must set the IDL bit in PCON register (see Table 10-3). The

AT8xC51SND2C enters Idle mode upon execution of the instruction that sets IDL bit. The

instruction that sets IDL bit is the last instruction executed.

Note:

If IDL bit and PD bit are set simultaneously, the AT8xC51SND2C enter Power-down mode. Then it

does not go in Idle mode when exiting Power-down mode.

10.3.2

Exiting Idle Mode

There are 2 ways to exit Idle mode:

Generate an enabled interrupt.

–

Hardware clears IDL bit in PCON register which restores the clock to the CPU.

Execution resumes with the interrupt service routine. Upon completion of the

interrupt service routine, program execution resumes with the instruction

immediately following the instruction that activated Idle mode. The general-purpose

flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt

occurred during normal operation or during Idle mode. When Idle mode is exited by

an interrupt, the interrupt service routine may examine GF1 and GF0.

Generate a reset.

–

A logic high on the RST pin clears IDL bit in PCON register directly and

asynchronously. This restores the clock to the CPU. Program execution momentarily

resumes with the instruction immediately following the instruction that activated the

Idle mode and may continue for a number of clock cycles before the internal reset

algorithm takes control. Reset initializes the AT8xC51SND2C and vectors the CPU

to address C:0000h.

Note:

During the time that execution resumes, the internal RAM cannot be accessed; however, it is pos-

sible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction

immediately following the instruction that activated Idle mode should not write to a Port pin or to

the external RAM.

10.4

Power-down Mode

The Power-down mode places the AT8xC51SND2C in a very low power state. Power-down

mode stops the oscillator and freezes all clocks at known states (refer to the Section "Oscillator",

page 13). The CPU status prior to entering Power-down mode is preserved, i.e., the program

counter, program status word register retain their data for the duration of Power-down mode. In

addition, the SFRs and RAM contents are preserved. The status of the Port pins during Power-

down mode is detailed in Table 10-1.

Note:

DD may be reduced to as low as VRET during Power-down mode to further reduce power dissipa-

tion. Notice, however, that V

DD is not reduced until Power-down mode is invoked.

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