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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT83SND2CMP3B датащи(PDF) 57 Page - ATMEL Corporation |
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AT83SND2CMP3B датащи(HTML) 57 Page - ATMEL Corporation |
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57 / 241 page  57 4341F–MP3–03/06 AT8xC51SND2C/MP3B 11.6 Registers Table 11-1. TCON Register TCON (S:88h) – Timer/Counter Control Register Reset Value = 0000 0000b 76 543 210 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7TF1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. 6TR1 Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. 5TF0 Timer 0 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows. 4TR0 Timer 0 Run Control Bit Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. 3IE1 Interrupt 1 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT1). Set by hardware when external interrupt is detected on INT1 pin. 2IT1 Interrupt 1 Type Control Bit Clear to select low level active (level triggered) for external interrupt 1 (INT1). Set to select falling edge active (edge triggered) for external interrupt 1. 1IE0 Interrupt 0 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0 pin. 0IT0 Interrupt 0 Type Control Bit Clear to select low level active (level triggered) for external interrupt 0 (INT0). Set to select falling edge active (edge triggered) for external interrupt 0. |
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