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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT83SND2CMP3B датащи(PDF) 83 Page - ATMEL Corporation |
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AT83SND2CMP3B датащи(HTML) 83 Page - ATMEL Corporation |
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83 / 241 page  83 4341F–MP3–03/06 AT8xC51SND2C/MP3B 15.1.2 Digital Signals Timing 15.1.2.1 Data Interface To avoid noises at the output, the reset state is maintained until proper synchronism is achieved in the DAC serial interface: •DSEL •SCLK • DCLK •DOUT The data interface allows three different data transfer modes: Figure 15-3. 20 bit I2S justified mode Figure 15-4. 20 bit MSB justified mode Figure 15-5. 20 bit LSB justified mode The selection between modes is done using the DINTSEL 1:0 in DAC_MISC register (Table 15- 22.) according with the following table: The data interface always works in slave mode. This means that the DSEL and the DCLK sig- nals are provided by microcontroller audio data interface. R1 R0 L(N-1) L(N-2) L(N-3) ... L2 L1 L0 R(N-1) R(N-2) R(N-3) ... R2 R1 R0 SCLK DSEL DOUT R0 L(N-1) L(N-2) L(N-3) ... L2 L1 L0 R(N-1) R(N-2) R(N-3) ... R2 R1 R0 L(N-1) SCLK DSEL DOUT R0 L(N-1) L(N-2) ... L1 L0 R(N-1) R(N-2) ... R1 R0 L(N-1) SCLK DSEL DOUT DINTSEL 1:0 Format 00 I2S Justified 01 MSB Justified 1x LSB Justified |
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